HM1-6514S-9 datasheet, PDF - EEWORLD Datasheet

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HM1-6514S-9: Description1KX4 STANDARD SRAM, 120ns, CDIP18, CERAMIC, DIP-18; Categorystorage storage; File Size85KB，7 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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HM1-6514S-9 Overview

1KX4 STANDARD SRAM, 120ns, CDIP18, CERAMIC, DIP-18

HM1-6514S-9 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Renesas Electronics Corporation
Parts packaging code	DIP
package instruction	DIP, DIP18,.3
Contacts	18
Reach Compliance Code	not_compliant
ECCN code	EAR99
Maximum access time	120 ns
Other features	LOW POWER STANDBY MODE; TTL COMPATIBLE INPUTS/OUTPUTS
I/O type	COMMON
JESD-30 code	R-GDIP-T18
JESD-609 code	e0
memory density	4096 bit
Memory IC Type	STANDARD SRAM
memory width	4
Number of functions	1
Number of terminals	18
word count	1024 words
character code	1000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	1KX4
Output characteristics	3-STATE
Package body material	CERAMIC, GLASS-SEALED
encapsulated code	DIP
Encapsulate equivalent code	DIP18,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
Maximum seat height	5.08 mm
Maximum standby current	0.000015 A
Minimum standby current	2 V
Maximum slew rate	0.031 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm

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HM-6514

1024 x 4 CMOS RAM

Description

The HM-6514 is a 1024 x 4 static CMOS RAM fabricated

using self-aligned silicon gate technology. The device uti-

lizes synchronous circuitry to achieve high performance and

low power operation.

On-chip latches are provided for addresses allowing efficient

interfacing with microprocessor systems. The data output

can be forced to a high impedance state for use in expanded

memory arrays.

Gated inputs allow lower operating current and also elimi-

nate the need for pull up or pull down resistors. The

HM-6514 is a fully static RAM and may be maintained in any

state for an indefinite period of time.

Data retention supply voltage and supply current are guaran-

teed over temperature.

March 1997

Features

• Low Power Standby. . . . . . . . . . . . . . . . . . . 125µW Max

• Low Power Operation . . . . . . . . . . . . . .35mW/MHz Max

• Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min

• TTL Compatible Input/Output

• Common Data Input/Output

• Three-State Output

• Standard JEDEC Pinout

• Fast Access Time . . . . . . . . . . . . . . . . . 120/200ns Max

• 18 Pin Package for High Density

• On-Chip Address Register

• Gated Inputs - No Pull Up or Pull Down Resistors

Required

Ordering Information

120ns

HM3-6514S-9

HM1-6514S-9

24502BVA

8102402VA

200ns

HM3-6514B-9

HM1-6514B-9

8102404VA

300ns

HM3-6514-9

HM1-6514-9

8102406VA

HM4-6514-B

TEMPERATURE RANGE

-40

C to +85

-40

C to +85

-40

C to +85

-55

C to +125

PACKAGE

PDIP

CERDIP

JAN#

SMD#

CLCC

PKG. NO.

E18.3

F18.3

J18.B

Pinouts

HM-6514 (PDIP, CERDIP)

TOP VIEW

GND

18 V

17 A7

16 A8

15 A9

14 DQ0

13 DQ1

12 DQ2

11 DQ3

10 W

HM-6514 (CLCC)

TOP VIEW

DESCRIPTION

Address Input

Chip Enable

Write Enable

16 A8

15 A9

14 DQ0

13 DQ1

12 DQ2

Data Input

Data Output

GND

DQ3

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

Intersil (and design) is a trademark of Intersil Americas Inc.

FN2995.1

HM1-6514S-9 Related Products

	HM1-6514S-9	HM3-6514-9	HM3-6514S-9	HM3-6514B-9	HM1-6514-9	HM4-6514-B
Description	1KX4 STANDARD SRAM, 120ns, CDIP18, CERAMIC, DIP-18	1KX4 STANDARD SRAM, 300ns, PDIP18	1KX4 STANDARD SRAM, 120ns, PDIP18, PLASTIC, DIP-18	1KX4 STANDARD SRAM, 220ns, PDIP18, PLASTIC, DIP-18	1KX4 STANDARD SRAM, 300ns, CDIP18	1KX4 STANDARD SRAM, 320ns, CQCC18, CERAMIC, LCC-18
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	Renesas Electronics Corporation	Renesas Electronics Corporation	Renesas Electronics Corporation	Renesas Electronics Corporation	Renesas Electronics Corporation	Renesas Electronics Corporation
Parts packaging code	DIP	DIP	DIP	DIP	DIP	LCC
package instruction	DIP, DIP18,.3	DIP, DIP18,.3	DIP, DIP18,.3	DIP, DIP18,.3	CERAMIC, DIP-18	QCCN,
Contacts	18	18	18	18	18	18
Reach Compliance Code	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	compliant
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	3A001.A.2.C
Maximum access time	120 ns	300 ns	120 ns	220 ns	300 ns	320 ns
Other features	LOW POWER STANDBY MODE; TTL COMPATIBLE INPUTS/OUTPUTS	ADDRESS LATCH; LOW POWER STANDBY MODE; TTL COMPATIBLE INPUTS/OUTPUTS	LOW POWER STANDBY MODE; TTL COMPATIBLE INPUTS/OUTPUTS	LOW POWER STANDBY MODE; TTL COMPATIBLE INPUTS/OUTPUTS	ADDRESS LATCH; LOW POWER STANDBY MODE; TTL COMPATIBLE INPUTS/OUTPUTS	LOW POWER STANDBY MODE; TTL COMPATIBLE INPUTS/OUTPUTS
JESD-30 code	R-GDIP-T18	R-PDIP-T18	R-PDIP-T18	R-PDIP-T18	R-GDIP-T18	R-CQCC-N18
JESD-609 code	e0	e0	e0	e0	e0	e0
memory density	4096 bit	4096 bit	4096 bit	4096 bit	4096 bit	4096 bit
Memory IC Type	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM
memory width	4	4	4	4	4	4
Number of functions	1	1	1	1	1	1
Number of terminals	18	18	18	18	18	18
word count	1024 words	1024 words	1024 words	1024 words	1024 words	1024 words
character code	1000	1000	1000	1000	1000	1000
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	125 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-55 °C
organize	1KX4	1KX4	1KX4	1KX4	1KX4	1KX4
Package body material	CERAMIC, GLASS-SEALED	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	CERAMIC, GLASS-SEALED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP	DIP	DIP	DIP	DIP	QCCN
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	IN-LINE	IN-LINE	IN-LINE	IN-LINE	CHIP CARRIER
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	NO	NO	NO	NO	NO	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	TIN LEAD
Terminal form	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	NO LEAD
Terminal pitch	2.54 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
I/O type	COMMON	COMMON	COMMON	COMMON	COMMON	-
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	-
Encapsulate equivalent code	DIP18,.3	DIP18,.3	DIP18,.3	DIP18,.3	DIP18,.3	-
power supply	5 V	5 V	5 V	5 V	5 V	-
Maximum seat height	5.08 mm	-	5.33 mm	5.33 mm	-	1.91 mm
Maximum standby current	0.000015 A	0.000015 A	0.000015 A	0.000015 A	0.000015 A	-
Minimum standby current	2 V	2 V	2 V	2 V	2 V	-
Maximum slew rate	0.031 mA	0.014 mA	0.031 mA	0.019 mA	0.014 mA	-
width	7.62 mm	-	7.62 mm	7.62 mm	-	7.43 mm

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