Freescale Semiconductor
Technical Data
MPC9653A
Rev 4, 10/2004
3.3 V 1:8 LVCMOS PLL Clock
Generator
The MPC9653A is a 3.3 V compatible, 1:8 PLL based clock generator and
zero-delay buffer targeted for high performance low-skew clock distribution in
mid-range to high-performance telecom, networking and computing applications.
With output frequencies up to 125 MHz and output skews less than 150 ps the
device meets the needs of the most demanding clock applications.
Features
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1:8 PLL based low-voltage clock generator
Supports zero-delay operation
3.3 V power supply
Generates clock signals up to 125 MHz
PLL guaranteed to lock down to 145 MHz, output frequency = 36.25 MHz
Maximum output skew of 150 ps
Differential LVPECL reference clock input
External PLL feedback
Drives up to 16 clock lines
32-lead LQFP packaging
32-lead Pb-free Package Available
Ambient temperature range 0°C to +70°C
Pin and function compatible to the MPC953 and MPC9653
MPC9653A
LOW VOLTAGE
3.3 V LVCMOS 1:8
PLL CLOCK GENERATOR
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
Functional Description
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
The MPC9653A utilizes PLL technology to frequency lock its outputs onto an
input reference clock. Normal operation of the MPC9653A requires the connec-
tion of the QFB output to the feedback input to close the PLL feedback path (external feedback). With the PLL locked, the output
frequency is equal to the reference frequency of the device and VCO_SEL selects the operating frequency range of 25 to
62.5 MHz or 50 to 125 MHz. The two available post-PLL dividers selected by VCO_SEL (divide-by-4 or divide-by-8) and the ref-
erence clock frequency determine the VCO frequency. Both must be selected to match the VCO frequency range. The internal
VCO of the MPC9653A is running at either 4x or 8x of the reference clock frequency. The MPC9653A is guaranteed to lock in a
low power PLL mode in the high frequency range (VCO_SEL = 0) down to PLL = 145 MHz or F
ref
= 36.25 MHz.
The MPC9653A has a differential LVPECL reference input along with an external feedback input. The device is ideal for use
as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance.
The PLL_EN and BYPASS controls select the PLL bypass configuration for test and diagnosis. In this configuration, the se-
lected input reference clock is bypassing the PLL and routed either to the output dividers or directly to the outputs. The PLL by-
pass configurations are fully static and the minimum clock frequency specification and all other PLL characteristics do not apply.
The outputs can be disabled (high-impedance) and the device reset by asserting the MR/OE pin. Asserting MR/OE also causes
the PLL to loose lock due to missing feedback signal presence at FB_IN. Deasserting MR/OE will enable the outputs and close
the phase locked loop, enabling the PLL to recover to normal operation.
The MPC9653A is fully 3.3 V compatible and requires no external loop filter components. The inputs (except PCLK) accept
LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50
Ω
transmission
lines. For series terminated transmission lines, each of the MPC9653A outputs can drive one or two traces giving the devices an
effective fanout of 1:16. The device is packaged in a 7x7 mm
2
32-lead LQFP package.
© Freescale Semiconductor, Inc., 2004. All rights reserved.
V
CC
2⋅25 k
PCLK
PCLK
0
&
Q0
÷
1
÷
2
0
0
1
÷
4
1
Q1
Q2
Q3
Q4
Q5
Ref
VCO
1
V
CC
25 k
FB_IN
V
CC
3⋅25 k
PLL_EN
VCO_SEL
BYPASS
MR/OE
25 k
PLL
1
200-500 MHz
FB
Q6
Q7
QFB
Note 1. PLL will lock @ 145 MHz
Figure 1. MPC9653A Logic Diagram
GND
24
GND
Q0
V
CC
QFB
GND
PLL_EN
BYPASS
VCO_SEL
25
26
27
28
29
30
31
32
1
23
22
21
20
19
18
GND
17
16
15
14
13
Q5
V
CC
Q6
GND
Q7
V
CC
MR/OE
PCLK
12
11
10
9
8
PCLK
V
CC
V
CC
6
NC
Q1
Q2
Q3
MPC9653A
2
3
4
5
V
CC_PLL
NC
NC
NC
Figure 2. MPC9653A 32-Lead Package Pinout
(Top View)
MPC9653A
2
Advanced Clock Drivers Device Data
Freescale Semiconductor
FB_IN
GND
Q4
7
Table 1. Pin Configuration
Pin
PCLK, PCLK
FB_IN
VCO_SEL
BYPASS
PLL_EN
MR/OE
Q0–7
QFB
GND
V
CC_PLL
V
CC
I/O
Input
Input
Input
Input
Input
Input
Output
Output
Supply
Supply
Supply
Type
LVPECL
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Ground
V
CC
V
CC
PECL reference clock signal
PLL feedback signal input, connect to QFB
Operating frequency range select
PLL and output divider bypass select
PLL enable/disable
Output enable/disable (high-impedance tristate) and device reset
Clock outputs
Clock output for PLL feedback, connect to FB_IN
Negative power supply (GND)
PLL positive power supply (analog power supply). It is recommended to use an external RC filter for
the analog power supply pin V
CC_PLL
. Refer to
APPLICATIONS INFORMATION
for details.
Positive power supply for I/O and core. All V
CC
pins must be connected to the positive power supply
for correct operation
Function
Table 2. Function Table
Control
PLL_EN
Default
1
0
Test mode with PLL bypassed. The reference clock (PCLK) Selects the VCO output
(1)
is substituted for the internal VCO output. MPC9653A is fully
static and no minimum frequency limit applies. All PLL
related AC characteristics are not applicable.
Test mode with PLL and output dividers bypassed. The
reference clock (PCLK) is directly routed to the outputs.
MPC9653A is fully static and no minimum frequency limit
applies. All PLL related AC characteristics are not
applicable.
VCO
÷
1 (High frequency range). f
REF
= f
Q0–7
= 4
⋅
f
VCO
Outputs enabled (active)
Selects the output dividers.
1
BYPASS
1
VCO_SEL
MR/OE
1
0
VCO
÷
2 (Low output range). f
REF
= f
Q0–7
= 8
⋅
f
VCO
Outputs disabled (high-impedance state) and reset of
the device. During reset the PLL feedback loop is open.
The VCO is tied to its lowest frequency. The length of the
reset pulse should be greater than one reference clock
cycle (PCLK).
1. PLL operation requires BYPASS = 1 and PLL_EN = 1.
MPC9653A
Advanced Clock Drivers Device Data
Freescale Semiconductor
3
Table 3. General Specifications
Symbol
V
TT
MM
HBM
LU
C
PD
C
IN
Characteristics
Output Termination Voltage
ESD Protection (Machine Model)
ESD Protection (Human Body Model)
Latch-Up Immunity
Power Dissipation Capacitance
Input Capacitance
200
2000
200
10
4.0
Min
Typ
V
CC
÷
2
Max
Unit
V
V
V
mA
pF
pF
Per output
Inputs
Condition
Table 4. Absolute Maximum Ratings
(1)
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
T
S
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage Temperature
–65
Characteristics
Min
–0.3
–0.3
–0.3
Max
3.9
V
CC
+ 0.3
V
CC
+ 0.3
±20
±50
125
Unit
V
V
V
mA
mA
°C
Condition
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Table 5. DC Characteristics
(V
CC
= 3.3 V ± 5%, T
A
= 0°C to 70°C)
Symbol
V
IH
V
IL
V
PP
V
CMR(1)
V
OH
V
OL
Z
OUT
I
IN
I
CC_PLL
I
CCQ(4)
Characteristics
Input high voltage
Input low voltage
Peak-to-peak input voltage
Common Mode Range
Output High Voltage
Output Low Voltage
Output impedance
Input Current
(3)
Maximum PLL Supply Current
Maximum Quiescent Supply Current
5.0
14 – 17
±200
10
10
(PCLK)
(PCLK)
300
1.0
2.4
0.55
0.30
V
CC
– 0.6
Min
2.0
Typ
Max
V
CC
+ 0.3
0.8
Unit
V
V
mV
V
V
V
V
Ω
µA
mA
mA
V
IN
= V
CC
or GND
V
CC_PLL
Pin
All V
CC
Pins
Condition
LVCMOS
LVCMOS
LVPECL
LVPECL
I
OH
= –24 mA
(2)
I
OL
= 24 mA
I
OL
= 12 mA
1. V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
CMR
range
and the input swing lies within the V
PP
(DC) specification.
2. The MPC9653A is capable of driving 50
Ω
transmission lines on the incident edge. Each output drives one 50
Ω
parallel terminated
transmission line to a termination voltage of V
TT
. Alternatively, the device drives up to two 50
Ω
series terminated transmission lines. The
MPC9653A meets the V
OH
and V
OL
specification of the MPC953 (V
OH
> V
CC
-0.6 V at I
OH
= -20 mA and V
OL
> 0.6 V at I
OL
= 20 mA).
3. Inputs have pull-down or pull-up resistors affecting the input current.
4. OE/MR = 1 (outputs in high-impedance state).
MPC9653A
4
Advanced Clock Drivers Device Data
Freescale Semiconductor
Table 6. AC Characteristics
(V
CC
= 3.3 V ± 5%, T
A
= 0°C to 70°C)
(1)
Symbol
f
REF
Characteristics
Input Reference Frequency
PLL Mode, External Feedback
÷
4 feedback
(2)
÷
8 feedback
(3)
Min
50
25
0
200
145
÷
4 feedback
(2)
÷
8 feedback
(3)
PCLK
PCLK
50
25
450
1.2
2
PCLK to FB_IN
–75
1.2
3.0
125
3.3
7.0
150
1.5
45
0.1
50
55
1.0
7.0
6.0
100
100
RMS (1σ)
÷
4 feedback
(2)
÷
8 feedback
(3)
25
0.8 – 4
0.5 – 1.3
10
Typ
Max
125
62.5
200
500
500
125
62.5
1000
V
CC
– 0.75
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
mV
V
ns
ps
ns
ns
ps
ns
%
ns
ns
ns
ps
ps
ps
MHz
MHz
ms
BYPASS = 0
PLL locked
0.55 to 2.4 V
PLL locked
PLL locked
PLL locked
LVPECL
LVPECL
Condition
PLL locked
PLL locked
Input reference frequency in PLL bypass mode
(4)
f
VCO
f
VCOlock
f
MAX
V
PP
V
CMR(8)
t
PW, MIN
t
(∅)
t
PD
VCO Operating Frequency Range
(5), (6)
VCO Lock Frequency Range
(7)
Output Frequency
Peak-to-Peak Input Voltage
Common Mode Range
Input Reference Pulse Width
(9)
Propagation Delay (static phase offset)
(10)
Propagation Delay
PLL and divider bypass (BYPASS = 0), PCLK to Q0–7
PLL disable (BYPASS = 1 and PLL_EN = 0), PCLK to Q0–7
Output-to-Output Skew
(11)
Device-to-Device Skew in PLL and Divider Bypass
(12)
Output Duty Cycle
Output Rise/Fall Time
Output Disable Time
Output Enable Time
Cycle-to-Cycle jitter
Period Jitter
I/O Phase Jitter
(13)
PLL closed loop bandwidth
(14)
PLL mode, external feedback
Maximum PLL Lock Time
t
sk(O)
t
sk(PP)
DC
t
R
, t
F
t
PLZ, HZ
t
PZL, LZ
t
JIT(CC)
t
JIT(PER)
t
JIT(∅)
BW
t
LOCK
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
AC characteristics apply for parallel output termination of 50
Ω
to V
TT
.
÷
4 PLL feedback (high frequency range) requires VCO_SEL = 0, PLL_EN = 1, BYPASS = 1 and MR/OE = 0.
÷
8 PLL feedback (low frequency range) requires VCO_SEL = 1, PLL_EN = 1, BYPASS = 1 and MR/OE = 0.
In bypass mode, the MPC9653A divides the input reference clock.
The input frequency f
REF
must match the VCO frequency range divided by the feedback divider ratio FB: f
REF
= f
VCO
÷
FB.
f
VCO
is frequency range where AC parameters are guaranteed.
f
VCOlock
is frequency range that the PLL guaranteed to lock, AC parameters only guaranteed over f
VCO
.
V
CMR
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
CMR
range
and the input swing lies within the V
PP
(AC) specification. Violation of V
CMR
or V
PP
impacts static phase offset t
(∅)
.
Calculation of reference duty cycle limits: DC
REF,MIN
= t
PW,MIN
⋅
f
REF
⋅
100% and DC
REF,MAX
= 100% - DC
REF,MIN
.
For example, at f
REF
= 100 MHz the input duty cycle range is 20% < DC < 80%.
Valid for f
REF
= 50 MHz and FB =
÷
8 (VCO_SEL = 1). For other reference frequencies: t
(∅)
[ps] = 50 ps
±
(1
÷
(120
⋅
f
REF
)).
Refer to the Application Information section for part-to-part skew calculation in PLL zero-delay mode.
For a specified temperature and voltage, includes output skew.
I/O phase jitter is reference frequency dependent. Refer to
APPLICATIONS INFORMATION
section for details.
–3 dB point of PLL transfer characteristics.
MPC9653A
Advanced Clock Drivers Device Data
Freescale Semiconductor
5
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