1CY7C1361A
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
256K x 36/512K x 18 Synchronous Burst Flowthrough SRAM
Features
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Fast access times: 6.0, 6.5, 7.0, and 8.0 ns
Fast clock speed: 150, 133, 117, and 100 MHz
1 ns set-up time and hold time
Fast OE access times: 3.5 ns and 4.0 ns
3.3V –5% and +10% power supply
3.3V or 2.5V I/O supply
5V tolerant inputs except I/Os
Clamp diodes to V
SS
at all inputs and outputs
Common data inputs and data outputs
Byte Write Enable and Global Write control
Multiple chip enables for depth expansion:
three chip enables for TA(GVTI)/A(CY) package version
and two chip enables for B(GVTI)/BG(CY) and
T(GVTI)/AJ(CY) package versions
Address pipeline capability
Address, data and control registers
Internally self-timed Write Cycle
Burst control pins (interleaved or linear burst se-
quence)
Automatic power-down for portable applications
JTAG boundary scan for B and T package version
Low profile 119-bump, 14-mm x 22-mm PBGA (Ball Grid
Array) and 100-pin TQFP packages
and a 2-bit counter for internal burst operation. All synchro-
nous inputs are gated by registers controlled by a positive-
edge-triggered Clock Input (CLK). The synchronous inputs in-
clude all addresses, all data inputs, address-pipelining Chip
Enable (CE), depth-expansion Chip Enables (CE
2
and CE
2
),
,
Burst Control Inputs (ADSC, ADSP and ADV), Write Enables
(BWa, BWb, BWc, BWd, and BWE), and Global Write (GW).
However, the CE
2
chip enable input is only available for TA(GV-
TI)/A(CY) package version.
Asynchronous inputs include the Output Enable (OE) and
burst mode control (MODE). The data outputs (Q), enabled by
OE, are also asynchronous.
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles can be one
to four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BWa
controls DQa. BWb controls DQb. BWc controls DQc. BWd
controls DQd. BWa, BWb, BWc, and BWd can be active only
with BWE being LOW. GW being LOW causes all bytes to be
written. The x18 version only has 18 data inputs/outputs (DQa
and DQb) along with BWa and BWb (no BWc, BWd, DQc, and
DQd).
For the B(GVTI)/BG(CY) and T(GVTI)/AJ(CY) package ver-
sions, four pins are used to implement JTAG test capabilities:
Test Mode Select (TMS), Test Data-In (TDI), Test Clock (TCK),
and Test Data-Out (TDO). The JTAG circuitry is used to serially
shift data to and from the device. JTAG inputs use
LVTTL/LVCMOS levels to shift data during this testing mode of
operation. The TA package version does not offer the JTAG
capability.
The GVT71256B36 and GVT71512B18 operate from a +3.3V
power supply. All inputs and outputs are LVTTL compatible.
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Functional Description
The Cypress Synchronous Burst SRAM family employs high-
speed, low-power CMOS designs using advanced triple-layer
polysilicon, double-layer metal technology. Each memory cell
consists of four transistors and two high-valued resistors.
The GVT71256B36/CY7C1361A and GVT71512B18/
CY7C1363A SRAMs integrate 262,144x36 and 524,288x18
SRAM cells with advanced synchronous peripheral circuitry
Selection Guide
7C1361A-150
7C1363A-150
71256B36-6
71512B18-6
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
6.0
400
10
7C1361A-133
7C1363A-133
71256B36-6.5
71512B18-6.5
6.5
360
10
7C1361A-117
7C1363A-117
71256B36-7
71512B18-7
7.0
320
10
7C1361A-100
7C1363A-100
71256B36-8
71512B18-8
8.0
270
10
Cypress Semiconductor Corporation
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3901 North First Street
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San Jose
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CA 95134
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408-943-2600
June 11, 2001
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
256K x 36 Pin Descriptions
x36 PBGA Pins
4P
4N
2A, 3A, 5A, 6A,
3B, 5B, 6B, 2C,
3C, 5C, 6C, 2R,
6R, 3T, 4T, 5T
x36 QFP Pins
37
36
35, 34, 33, 32,
100, 99, 82, 81,
44, 45, 46, 47,
48, 49, 50
92 (A/T version)
43 (AJ/TA ver-
sion)
93
94
95
96
87
Pin
Name
A0
A1
A
Type
Input-
Synchronous
Description
Addresses: These inputs are registered and must meet the set-
up and hold times around the rising edge of CLK. The burst
counter generates internal addresses associated with A0 and A1,
during burst cycle and wait cycle.
5L
5G
3G
3L
4M
BWa
BWb
BWc
BWd
BWE
Input-
Synchronous
Byte Write: A byte write is LOW for a WRITE cycle and HIGH for
a READ cycle. BWa controls DQa. BWb controls DQb. BWc con-
trols DQc. BWd controls DQd. Data I/O are high impedance if
either of these inputs are LOW, conditioned by BWE being LOW.
Write Enable: This active LOW input gates byte write operations
and must meet the set-up and hold times around the rising edge
of CLK.
Global Write: This active LOW input allows a full 36-bit WRITE to
occur independent of the BWE and BWn lines and must meet the
set up and hold times around the rising edge of CLK.
Clock: This signal registers the addresses, data, chip enables,
write control and burst control inputs on its rising edge. All syn-
chronous inputs must meet set up and hold times around the
clock’s rising edge.
Chip Enable: This active LOW input is used to enable the device
.
and to gate ADSP
Chip Enable: This active HIGH input is used to enable the device.
Chip Enable: This active LOW input is used to enable the device.
Not available for B and T package versions.
Output Enable: This active LOW asynchronous input enables the
data output drivers.
Address Advance: This active LOW input is used to control the
internal burst counter. A HIGH on this pin generates wait cycle
(no address advance).
Address Status Processor: This active LOW input, along with CE
being LOW, causes a new external address to be registered and
a READ cycle is initiated using the new address.
Address Status Controller: This active LOW input causes device
to be deselected or selected along with new external address to
be registered. A READ or WRITE cycle is initiated depending
upon write control inputs.
Mode: This input selects the burst sequence. A LOW on this pin
selects linear burst. A NC or HIGH on this pin selects interleaved
burst.
Snooze: This active HIGH input puts the device in low power
consumption standby mode. For normal operation, this input has
to be either LOW or NC (No Connect).
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
4H
88
GW
4K
89
CLK
4E
2B
(not available for
PBGA)
4F
4G
98
97
92 (for AJ/TA
version only)
86
83
CE
CE
2
CE
2
OE
ADV
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
4A
84
ADSP
4B
85
ADSC
3R
31
MODE
Input-
Static
Input-
Asynchro-
nous
7T
64
ZZ
5
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