GS8182D37BD-435MT datasheet, PDF

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GS8182D37BD-435MT: DescriptionQDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FPBGA-165; Categorystorage storage; File Size372KB，28 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/

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GS8182D37BD-435MT Overview

QDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FPBGA-165

GS8182D37BD-435MT Parametric

Parameter Name	Attribute value
Maker	GSI Technology
Parts packaging code	BGA
package instruction	LBGA,
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Maximum access time	0.45 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165
length	15 mm
memory density	18874368 bit
Memory IC Type	QDR SRAM
memory width	36
Number of functions	1
Number of terminals	165
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	512KX36
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	1.4 mm
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	13 mm

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GS8182D19/37BD-435M

165-Bump BGA

Military Temp

Features

• Military Temperature Range

• 2.0 Clock Latency

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• Burst of 4 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• Data Valid Pin (QVLD)

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package

18Mb SigmaQuad-II+

Burst of 4 SRAM

435 MHz

1.8 V V

1.8 V and 1.5 V I/O

element in a family of low power, low voltage HSTL I/O

SRAMs designed to operate at the speeds needed to implement

economical high performance networking systems.

Clocking and Addressing Schemes

The GS8182D19/37BD-435M SigmaQuad-II+ SRAM is a

synchronous device. It employs two input register clock inputs,

K and K. K and K are independent single-ended clock inputs,

not differential inputs to a single differential clock input buffer.

Each internal read and write operation in a SigmaQuad-II+ B4

RAM is four times wider than the device I/O bus. An input

data bus de-multiplexer is used to accumulate incoming data

before it is simultaneously written to the memory array. An

output data multiplexer is used to capture the data produced

from a single memory array read and then route it to the

appropriate output drivers as needed. Therefore the address

field of a SigmaQuad-II+ B4 RAM is always two address pins

less than the advertised index depth (e.g., the 2M x 8 has a

512K addressable index).

SigmaQuad™ Family Overview

The GS8182D19/37BD-435M is built in compliance with the

SigmaQuad-II+ SRAM pinout standard for Separate I/O

synchronous SRAMs. It is a 18,874,368-bit (18Mb) SRAMs.

The GS8182D19/37BD-435M SigmaQuad SRAM is just one

Parameter Synopsis

-435M

tKHKH

tKHQV

2.3 ns

0.45 ns

Rev: 1.00a 11/2011

1/28

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8182D37BD-435MT Related Products

	GS8182D37BD-435MT	GS8182D19BD-435M	GS8182D19BD-435MT	GS8182D37BD-435M
Description	QDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FPBGA-165	QDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FPBGA-165	QDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FPBGA-165	QDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FPBGA-165
Parts packaging code	BGA	BGA	BGA	BGA
package instruction	LBGA,	LBGA,	LBGA,	LBGA,
Contacts	165	165	165	165
Reach Compliance Code	compliant	compliant	compliant	compliant
ECCN code	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B
Maximum access time	0.45 ns	0.45 ns	0.45 ns	0.45 ns
Other features	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165
length	15 mm	15 mm	15 mm	15 mm
memory density	18874368 bit	18874368 bit	18874368 bit	18874368 bit
Memory IC Type	QDR SRAM	QDR SRAM	QDR SRAM	QDR SRAM
memory width	36	18	18	36
Number of functions	1	1	1	1
Number of terminals	165	165	165	165
word count	524288 words	1048576 words	1048576 words	524288 words
character code	512000	1000000	1000000	512000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C	-55 °C
organize	512KX36	1MX18	1MX18	512KX36
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LBGA	LBGA	LBGA	LBGA
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.4 mm	1.4 mm	1.4 mm	1.4 mm
Maximum supply voltage (Vsup)	1.9 V	1.9 V	1.9 V	1.9 V
Minimum supply voltage (Vsup)	1.7 V	1.7 V	1.7 V	1.7 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	MILITARY	MILITARY
Terminal form	BALL	BALL	BALL	BALL
Terminal pitch	1 mm	1 mm	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM
width	13 mm	13 mm	13 mm	13 mm
Maker	GSI Technology	-	GSI Technology	GSI Technology

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