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M965G0225MP0-C70

Description
Synchronous Graphics RAM Module, 2MX64, 5.5ns, CMOS, SODIMM-144
Categorystorage    storage   
File Size363KB,14 Pages
ManufacturerSAMSUNG
Websitehttp://www.samsung.com/Products/Semiconductor/
Download Datasheet Parametric View All

M965G0225MP0-C70 Overview

Synchronous Graphics RAM Module, 2MX64, 5.5ns, CMOS, SODIMM-144

M965G0225MP0-C70 Parametric

Parameter NameAttribute value
MakerSAMSUNG
Parts packaging codeMODULE
package instructionDIMM, DIMM144,32
Contacts144
Reach Compliance Codecompliant
ECCN codeEAR99
access modeDUAL BANK PAGE BURST
Maximum access time5.5 ns
Other featuresAUTO/SELF REFRESH
Maximum clock frequency (fCLK)143 MHz
I/O typeCOMMON
JESD-30 codeR-XDMA-N144
memory density134217728 bit
Memory IC TypeSYNCHRONOUS GRAPHICS RAM MODULE
memory width64
Number of functions1
Number of ports1
Number of terminals144
word count2097152 words
character code2000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize2MX64
Output characteristics3-STATE
Package body materialUNSPECIFIED
encapsulated codeDIMM
Encapsulate equivalent codeDIMM144,32
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
power supply3.3 V
Certification statusNot Qualified
refresh cycle2048
self refreshYES
Maximum standby current0.008 A
Maximum slew rate0.64 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formNO LEAD
Terminal pitch0.8 mm
Terminal locationDUAL
SGRAM MODULE
M965G0225MP(Q)0 / M966G0225MP(Q)0
M965G0225MP(Q)0 / M966G0225MP(Q)0 SGRAM SODIMM
2Mx64 SGRAM SODIMM based on 1Mx32, 2K Refresh, 3.3V Synchronous Graphic RAMs
GENERAL DESCRIPTION
The Samsung M965(6)G0225MP(Q)0 is a 2M bit x 64 Syn-
chronous Graphic RAM high density memory module. The
Samsung M965(6)G0225MP(Q)0 consists of four CMOS 1M x
32 bit Synchronous Graphic RAMs in 100pin QFP packages
mounted on a 144pin glass-epoxy substrate. Five 0.1uF
decoupling capacitors are mounted on the printed circuit board
for each Synchronous GRAM. The M965(6)G0225MP(Q)0 is a
Small Outline Dual In-line Memory Module and is intended for
mounting into 144-pin edge connector sockets.
Synchronous design allows precise cycle control with the use
of system clock. I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable laten-
cies and burst lengths allows the same device to be useful for a
variety of high bandwidth, high performance memory system
applications.
FEATURE
• Performance range
Part NO.
M965(6)G0225MP(Q)0-C50
M965(6)G0225MP(Q)0-C60
M965(6)G0225MP(Q)0-C70
M965(6)G0225MP(Q)0-C80
Max. Freq. (t
CC
)
200MHz (5ns) @CL=3
166MHz (6ns) @CL=3
143MHz (7ns) @CL=3
125MHz (8ns) @CL=3
* M965(6)G0225MP0 : based on PQFP Component
M965(6)G0225MQ0 : based on TQFP Component
Burst Mode Operation
BLOCK-WRITE and Write-per-bit capability
Independent byte operation via DQM0 ~ 7
Auto & Self Refresh Capability (2048 cycles / 32ms)
LVTTL compatible inputs and outputs
Single 3.3V±0.3V power supply
MRS cycle with address key programs.
CAS Latency (2, 3)
Burst Length (1, 2, 4, 8 & Full page)
Data Scramble (Sequential & Interleave)
• Optional Serial PD with EEPROM (M966G0225)
• Resistor Strapping Options for speed and CAS Latency
• PCB : Height(1250mil), double sided components
PIN CONFIGURATIONS (Front Side / Back Side)
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Front
V
SS
DQ63
DQ61
DQ59
DQ57
V
DD
DQ55
DQ53
DQ51
DQ49
V
SS
DQM7
DQM5
V
DD
DQ47
DQ45
DQ43
DQ41
V
SS
DQ39
DQ37
DQ35
DQ33
V
DD
RSVD
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Back
V
SS
DQ62
DQ60
DQ58
DQ56
V
DD
DQ54
DQ52
DQ50
DQ48
V
SS
DQM6
DQM4
V
DD
DQ46
DQ44
DQ42
DQ40
V
SS
DQ38
DQ36
DQ34
DQ32
V
DD
RSVD
Pin
Front
Pin
Back
Pin
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
Front
DQ31
DQ29
DQ27
DQ25
V
SS
DQ23
DQ21
DQ19
DQ17
V
DD
DQM3
DQM1
V
SS
DQ15
DQ13
DQ11
DQ9
V
DD
DQ7
DQ5
DQ3
DQ1
V
SS
**SDA
V
DD
Pin
Back
PIN NAMES
Pin Name
A0 ~ A10
BA
DQ0 ~ 63
CLK0, CLK1
CKE
CS0, CS1
RAS
CAS
WE
DSF
DQM0 ~ 7
V
DD
V
SS
**SDA
**SBA
**SCL
RSVD
RFU
NC
Function
Address Input(multiplexed)
Bank Select Address
Data Input / Output
Clock Input
Clock Enable Input
Chip Select Input
Row Address Strobe
Column Address Strobe
Write Enable
Define Special Function
DQM
Power Supply (3.3V)
Ground
Serial Address Data I/O
EEPROM Device Address
Serial Clock
Reserved
Reserved for future use
No Connection
96 DQ30
98 DQ28
100 DQ26
102 DQ24
104
V
SS
106 DQ22
108 DQ20
110 DQ18
112 DQ16
114
V
DD
116 DQM2
118 DQM0
120
V
SS
122 DQ14
124 DQ12
126 DQ10
128 DQ8
130
V
DD
132 DQ6
134 DQ4
136 DQ2
138 DQ0
140
V
SS
142 **SCL
144
V
DD
Voltage Key
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
RSVD
RSVD
V
SS
DSF
RFU
RFU
V
DD
CS1
RAS
WE
V
SS
CLK1
V
DD
RSVD
A10
BA
A7
V
SS
A5
A3
A1
V
DD
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
RSVD
RSVD
V
SS
RFU
RFU
**SBA
V
DD
CS0
CAS
CKE
V
SS
CLK0
V
DD
RSVD
A9
A8/AP
A6
V
SS
A4
A2
A0
V
DD
**
These pins should be NC in the system
which does not support SPD.
SAMSUNG ELECTRONICS CO. Ltd. reserves the right to change products and specifications without notice.
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