CY7C1387B-167BZI datasheet, PDF

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CY7C1387B-167BZI: DescriptionCache SRAM, 1MX18, 3.4ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165; Categorystorage storage; File Size519KB，32 Pages; ManufacturerCypress Semiconductor

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CY7C1387B-167BZI Overview

Cache SRAM, 1MX18, 3.4ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165

CY7C1387B-167BZI Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Cypress Semiconductor
Parts packaging code	BGA
package instruction	13 X 15 MM, 1.20 MM HEIGHT, FBGA-165
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	3.4 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	167 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B165
JESD-609 code	e0
length	15 mm
memory density	18874368 bit
Memory IC Type	CACHE SRAM
memory width	18
Humidity sensitivity level	3
Number of functions	1
Number of terminals	165
word count	1048576 words
character code	1000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	1MX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	220
power supply	2.5/3.3,3.3 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum standby current	0.02 A
Minimum standby current	3.14 V
Maximum slew rate	0.285 mA
Maximum supply voltage (Vsup)	3.63 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	13 mm

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86B

CY7C1386B

CY7C1387B

512K x 36/1M x 18 Pipelined DCD SRAM

Features

•

Fast clock speed: 200, 167, 150, 133 MHz

Provide high-performance 3-1-1-1 access rate

Fast OE access times: 3.0, 3.4, 3.8, and 4.2 ns

Optimal for depth expansion

3.3V (–5%/+10%) power supply

Common data inputs and data outputs

Byte Write Enable and Global Write control

Double-cycle deselect

Chip enable for address pipeline

Address, data, and control registers

Internally self-timed Write cycle

Burst control pins (interleaved or linear burst

sequence)

Automatic power-down available using ZZ mode or CE

deselect

High-density, high-speed packages

JTAG boundary scan for BGA packaging version

Automatic power down available using ZZ mode or CE

deselect

registers controlled by a positive-edge-triggered Clock Input

(CLK). The synchronous inputs include all addresses, data

inputs, address-pipelining Chip Enables (CEs), burst control

inputs (ADSC, ADSP, and ADV), Write Enables (BWa, BWb,

BWc, BWd and BWE), and Global Write (GW).

Asynchronous inputs include the Output Enable (OE) and

burst mode control (MODE). DQ

a,b,c,d

and DP

a,b,c,d

apply to

CY7C1386B and DQ

a,b

and DP

a,b

apply to CY7C1387B. a, b,

c, and d each are 8 bits wide in the case of DQ and 1 bit wide

in the case of DP.

Addresses and chip enables are registered with either

Address Status Processor (ADSP) or Address Status

Controller (ADSC) input pins. Subsequent burst addresses

can be internally generated as controlled by the Burst Advance

Pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate self-timed Write cycles. Write cycles can be one to

four bytes wide as controlled by the write control inputs.

Individual byte write allows individual byte to be written. BWa

controls DQa and DQPa. BWb controls DQb and DQPb. BWc

controls DQc and DQPd. BWd controls DQd–DQd and DQPd.

BWa, BWb, BWc, and BWd can be active only with BWE LOW.

GW LOW causes all bytes to be written. Write pass-through

capability allows written data available at the output for the

immediately next Read cycle. This device also incorporates

pipelined enable circuit for easy depth expansion without

penalizing system performance.

The CY7C1386B and CY7C1387B are both double-cycle

deselect parts. All inputs and outputs of the CY7C1386B and

the CY7C1387B are JEDEC-standard JESD8-5-compatible.

Functional Description

The Cypress Synchronous Burst SRAM family employs

high-speed, low-power CMOS designs using advanced

single-layer polysilicon, triple-layer metal technology. Each

memory cell consists of six transistors.

The CY7C1386B and CY7C1387B SRAMs integrate

524,288 × 36 and 1,048,576 × 18 SRAM cells with advanced

synchronous peripheral circuitry and a 2-bit counter for

internal burst operation. All synchronous inputs are gated by

Selection Guide

200 MHz

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

315

167 MHz

3.4

285

150 MHz

3.8

265

133 MHz

4.2

245

Unit

Cypress Semiconductor Corporation

Document #: 38-05195 Rev. *C

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised January 18, 2003

CY7C1387B-167BZI Related Products

	CY7C1387B-167BZI	CY7C1387B-167AI	CY7C1387B-167BGI	CY7C1387B-133AI
Description	Cache SRAM, 1MX18, 3.4ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165	Cache SRAM, 1MX18, 3.4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100	Cache SRAM, 1MX18, 3.4ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119	Cache SRAM, 1MX18, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible
Maker	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor
Parts packaging code	BGA	QFP	BGA	QFP
package instruction	13 X 15 MM, 1.20 MM HEIGHT, FBGA-165	14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100	14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119	14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
Contacts	165	100	119	100
Reach Compliance Code	compliant	not_compliant	not_compliant	not_compliant
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Maximum access time	3.4 ns	3.4 ns	3.4 ns	4.2 ns
Other features	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	167 MHz	167 MHz	167 MHz	133 MHz
I/O type	COMMON	COMMON	COMMON	COMMON
JESD-30 code	R-PBGA-B165	R-PQFP-G100	R-PBGA-B119	R-PQFP-G100
JESD-609 code	e0	e0	e0	e0
length	15 mm	20 mm	22 mm	20 mm
memory density	18874368 bit	18874368 bit	18874368 bit	18874368 bit
Memory IC Type	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM
memory width	18	18	18	18
Number of functions	1	1	1	1
Number of terminals	165	100	119	100
word count	1048576 words	1048576 words	1048576 words	1048576 words
character code	1000000	1000000	1000000	1000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C
organize	1MX18	1MX18	1MX18	1MX18
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TBGA	LQFP	BGA	LQFP
Encapsulate equivalent code	BGA165,11X15,40	BGA165,11X15,40	BGA119,7X17,50	BGA165,11X15,40
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE	FLATPACK, LOW PROFILE	GRID ARRAY	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	220	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.6 mm	2.4 mm	1.6 mm
Maximum standby current	0.02 A	0.02 A	0.02 A	0.02 A
Minimum standby current	3.14 V	3.14 V	3.14 V	3.14 V
Maximum slew rate	0.285 mA	0.285 mA	0.285 mA	0.245 mA
Maximum supply voltage (Vsup)	3.63 V	3.63 V	3.63 V	3.63 V
Minimum supply voltage (Vsup)	3.135 V	3.135 V	3.135 V	3.135 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	BALL	GULL WING	BALL	GULL WING
Terminal pitch	1 mm	0.65 mm	1.27 mm	0.65 mm
Terminal location	BOTTOM	QUAD	BOTTOM	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	13 mm	14 mm	14 mm	14 mm

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