EEWORLDEEWORLDEEWORLD

Part Number

Search
 PDF

JDLGLMUT-FREQ

Description
VCXO, CLOCK, 15 MHz - 170 MHz, PECL OUTPUT, HERMETICALLY SEALED, CERAMIC, SO-6
CategoryPassive components    oscillator   
File Size113KB,8 Pages
ManufacturerVectron International, Inc.
Websitehttp://www.vectron.com/
Environmental Compliance  
Download Datasheet Parametric View All

JDLGLMUT-FREQ Overview

VCXO, CLOCK, 15 MHz - 170 MHz, PECL OUTPUT, HERMETICALLY SEALED, CERAMIC, SO-6

JDLGLMUT-FREQ Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerVectron International, Inc.
Reach Compliance Codecompliant
Maximum control voltage3 V
Minimum control voltage0.3 V
maximum descent time1 ns
Frequency Adjustment - MechanicalNO
Frequency offset/pull rate50 ppm
JESD-609 codee4
linearity10%
Manufacturer's serial numberJ
Installation featuresSURFACE MOUNT
Maximum operating frequency170 MHz
Minimum operating frequency15 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typePECL
physical size13.97mm x 8.89mm x 3.47mm
longest rise time1 ns
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry45/55 %
Terminal surfaceGOLD OVER NICKEL
Baseband and RF design in mobile phones
This is an English article. Those who are interested can use it as a reference....
yh19782000 RF/Wirelessly
HT46R23 AD conversion application source code
HT46R23 AD conversion application source program, all holtek chips AD program can refer to this program, such as HT46R47, HT46R22, HT46R24, HT36R62, HT46R64, HT46R65...
rain Test/Measurement
Anyone knows about LTC6811?
LTC6811 is used in BMS, but I don't know much about it. Can anyone share some information? Thank you....
Enid. Analog electronics
Python Notes for Professionals book
Free eBook Python Notes for Professionals bookhttps://download.eeworld.com.cn/detail/dcexpert/624785...
dcexpert Download Centre
Design of low voltage SRAM unit circuit based on 28nm process
Based on the analysis of the working principle of traditional SRAM memory cells, the static noise margin is measured by using VTC butterfly curve, word line voltage drive, bit line voltage drive and N...
是酒窝啊 FPGA/CPLD
~\(≧▽≦)/~A new board just arrived today, you know~
There is no engineer who doesn't want a board~~Houhou, there are quite a lot of new boards recently~~ Another new board arrived today~~You know~Let me first unbox and show you~Board in hand~ Qinheng i...
okhxyyo Domestic Chip Exchange

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号