Preliminary
GS880F18/36T-10/11/11.5/12/14
100 Pin TQFP
Commercial Temp
Industrial Temp
Features
• Flow through mode operation.
• 3.3V +10%/-5% Core power supply.
• 2.5V or 3.3V I/O supply.
• LBO pin for linear or interleaved burst mode.
• Internal input resistors on mode pins allow floating mode pins.
Default to Interleaved Pipelined Mode.
• Byte write (BW) and/or global write (GW) operation.
• Common data inputs and data outputs.
• Clock Control, registered, address, data, and control.
• Internal Self-Timed Write cycle.
• Automatic power-down for portable applications.
• 100-lead TQFP package
-10
-11
-11.5
-12
-14
10ns 11ns 11.5ns 12ns 14ns
Flow Through t
KQ
2-1-1-1
tCycle 10ns 15ns 15ns 15ns 15ns
I
DD
225mA 180mA 180mA 180mA 175mA
512K x 18, 256K x 36
8Mb Sync Burst SRAMs
10ns - 14ns
3.3V VDD
3.3V & 2.5V I/O
broadest access to multiple vendor sources. Boards designed with FT
pin pads tied low may be stuffed with GSI’s Pipeline/Flow through
configurable Burst RAMS or any vendor’s Flow through or
configurable Burst SRAM. Bumps designed with the FT pin location
tied High or floating must employ a non-configurable Flow through
Burst RAM, like this RAM, to achieve Flow through functionality.
88018/32/36T
Byte Write and Global Write
Byte write operation is performed by using byte write enable (BW)
input combined with one or more individual byte write signals (Bx). In
addition, Global Write (GW) is available for writing all bytes at one
time, regardless of the Byte Write control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of
the ZZ signal, or by stopping the clock (CK). Memory data is retained
during Sleep mode.
Core and Interface Voltages
The GS880F18/32/36T operates on a 3.3V power supply and all
inputs/outputs are 3.3V and 2.5V compatible. Separate output power
(V
DDQ
) pins are used to de-couple output noise from the internal
circuit.
Functional Description
Applications
The GS880F18/32/36T is a 9,437,184 bit (8,388,608 bit for x32
version) high performance synchronous SRAM with a 2 bit burst
address counter. Although of a type originally developed for Level 2
Cache applications supporting high performance CPU’s, the device
now finds application in synchronous SRAM applications ranging from
DSP main store to networking chip set support.
Controls
Addresses, data I/O’s, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive edge triggered
clock input (CK). Output enable (G) and power down control (ZZ) are
asynchronous inputs. Burst cycles can be initiated with either ADSP
or ADSC inputs. In Burst mode, subsequent burst addresses are
generated internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or interleave order
with the Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Designing For Compatibility
The JEDEC Standard for Burst RAMS calls for a FT mode pin option
(pin 14 on TQFP). Board sites for Flow through Burst RAMS should
be designed with V
SS
connected to the FT pin location to ensure the
Rev: 1.03 3/2000
1/25
© 2000, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880F18/36T-10/11/11.5/12/14
GS880F18 100 Pin TQFP Pinout
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQ
B1
DQ
B2
V
SS
V
DDQ
DQ
B3
DQ
B4
NC
V
DD
NC
V
SS
DQ
B5
DQ
B6
V
DDQ
V
SS
DQ
B7
DQ
B8
DQ
B9
NC
V
SS
V
DDQ
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
512K x 18
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
CK
GW
BW
G
ADSC
ADSP
ADV
A
8
A
9
A
6
A
7
E
1
E
2
NC
NC
B
B
B
A
E
3
V
DD
V
SS
A
18
NC
NC
V
DDQ
V
SS
NC
DQ
A9
DQ
A8
DQ
A7
V
SS
V
DDQ
DQ
A6
DQ
A5
V
SS
NC
V
DD
ZZ
DQ
A4
DQ
A3
V
DDQ
V
SS
DQ
A2
DQ
A1
NC
NC
V
SS
V
DDQ
NC
NC
NC
LBO
A
5
A
4
A
3
A
2
A
1
A
0
NC
NC
V
SS
V
DD
NC
A
17
A
10
A
11
A
12
A
13
A
14
A
15
2/25
Rev: 1.03 3/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
A
16
© 2000, Giga Semiconductor, Inc.
N
Preliminary
GS880F18/36T-10/11/11.5/12/14
GS880F32 100 Pin TQFP Pinout
NC
DQ
C8
DQ
C7
V
DDQ
V
SS
DQ
C6
DQ
C5
DQ
C4
DQ
C3
V
SS
V
DDQ
DQ
C2
DQ
C1
NC
V
DD
NC
V
SS
DQ
D1
DQ
D2
V
DDQ
V
SS
DQ
D3
DQ
D4
DQ
D5
DQ
D6
V
SS
V
DDQ
DQ
D7
DQ
D8
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
256K x 32
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
CK
GW
BW
G
ADSC
ADSP
ADV
A
8
A
9
A
6
A
7
E
1
E
2
B
D
B
C
B
B
B
A
E
3
V
DD
V
SS
NC
DQ
B8
DQ
B7
V
DDQ
V
SS
DQ
B6
DQ
B5
DQ
B4
DQ
B3
V
SS
V
DDQ
DQ
B2
DQ
B1
V
SS
NC
V
DD
ZZ
DQ
A1
DQ
A2
V
DDQ
V
SS
DQ
A3
DQ
A4
DQ
A5
DQ
A6
V
SS
V
DDQ
DQ
A7
DQ
A8
NC
LBO
A
5
A
4
A
3
A
2
A
1
A
0
NC
NC
V
SS
V
DD
NC
A
17
A
10
A
11
A
12
A
13
A
14
A
15
3/25
Rev: 1.03 3/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
A
16
© 2000, Giga Semiconductor, Inc.
N
Preliminary
GS880F18/36T-10/11/11.5/12/14
GS880F36 100 Pin TQFP Pinout
DQ
C9
DQ
C8
DQ
C7
V
DDQ
V
SS
DQ
C6
DQ
C5
DQ
C4
DQ
C3
V
SS
V
DDQ
DQ
C2
DQ
C1
NC
V
DD
NC
V
SS
DQ
D1
DQ
D2
V
DDQ
V
SS
DQ
D3
DQ
D4
DQ
D5
DQ
D6
V
SS
V
DDQ
DQ
D7
DQ
D8
DQ
D9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
256K x 36
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
CK
GW
BW
G
ADSC
ADSP
ADV
A
8
A
9
A
6
A
7
E
1
E
2
B
D
B
C
B
B
B
A
E
3
V
DD
V
SS
DQ
B9
DQ
B8
DQ
B7
V
DDQ
V
SS
DQ
B6
DQ
B5
DQ
B4
DQ
B3
V
SS
V
DDQ
DQ
B2
DQ
B1
V
SS
NC
V
DD
ZZ
DQ
A1
DQ
A2
V
DDQ
V
SS
DQ
A3
DQ
A4
DQ
A5
DQ
A6
V
SS
V
DDQ
DQ
A7
DQ
A8
DQ
A9
LBO
A
5
A
4
A
3
A
2
A
1
A
0
NC
NC
V
SS
V
DD
NC
A
17
A
10
A
11
A
12
A
13
A
14
A
15
4/25
Rev: 1.03 3/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
A
16
© 2000, Giga Semiconductor, Inc.
N
Preliminary
GS880F18/36T-10/11/11.5/12/14
TQFP Pin Description
Pin Location
37, 36
35, 34, 33, 32, 100, 99, 82, 81, 44, 45,
46, 47, 48, 49, 50, 43
80
63, 62, 59, 58, 57, 56, 53, 52
68, 69, 72, 73, 74, 75, 78, 79
13, 12, 9, 8, 7, 6, 3, 2
18, 19, 22, 23, 24, 25, 28, 29
51, 80, 1, 30
51, 80, 1, 30
58, 59, 62, 63, 68, 69, 72, 73, 74
8, 9, 12, 13, 18, 19, 22, 23, 24
51, 52, 53, 56, 57
75, 78, 79,
1, 2, 3, 6, 7
25, 28, 29, 30
16
66
87
93, 94
95, 96
95, 96
89
88
98, 92
97
86
83
84, 85
64
31
15, 41, 65, 91
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90
4, 11, 20, 27, 54, 61, 70, 77
14, 16, 38, 39, 42, 66
Symbol
A
0
, A
1
A
2
-
17
A
18
DQ
A1
-DQ
A8
DQ
B1
-DQ
B8
DQ
C1
-DQ
C8
DQ
D1
-DQ
D8
DQ
A9
, DQ
B9
,
DQ
C9
, DQ
D9
NC
DQ
A1
-DQ
A9
DQ
B1
- DQ
B9
NC
DP
QE
BW
B
A
, B
B
B
C
, B
D
NC
CK
GW
E
1
, E
3
E
2
G
ADV
ADSP, ADSC
ZZ
LBO
V
DD
V
SS
V
DDQ
NC
Type
I
I
I
I/O
Description
Address field LSB’s and Address Counter preset Inputs
Address Inputs
Address Inputs
Data Input and Output pins. (x32, x36 Version)
I/O
-
I/O
Data Input and Output pins.
No Connect (x32 Version)
Data Input and Output pins.
-
I
O
I
I
I
-
I
I
I
I
I
I
I
I
I
I
I
I
-
No Connect
Parity Input. 1 = Even, 0 = Odd.
Parity Error Out. Open Drain Output.
Byte Write. Writes all enabled bytes. Active Low.
Byte Write Enable for DQ
A
, DQ
B
Data I/O’s. Active Low.
Byte Write Enable for DQ
C
, DQ
D
Data I/O’s. Active Low. (x32, x36
Version)
No Connect (x18 Version)
Clock Input Signal. Active High.
Global Write Enable. Writes all bytes. Active Low.
Chip Enable. Active Low.
Chip Enable. Active High.
Output Enable. Active Low.
Burst address counter advance enable. Active Low.
Address Strobe (Processor, Cache Controller). Active Low.
Sleep Mode control. Active High.
Linear Burst Order mode. Active Low.
Core power supply.
I/O and Core Ground.
Output driver power supply.
No Connect.
Rev: 1.03 3/2000
5/25
© 2000, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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