EE PLD, 4.5ns, CMOS, PBGA100
| Parameter Name | Attribute value |
| Is it Rohs certified? | incompatible |
| Maker | Intel |
| package instruction | BGA, |
| Reach Compliance Code | compliant |
| maximum clock frequency | 250 MHz |
| JESD-30 code | S-PBGA-B100 |
| JESD-609 code | e0 |
| Dedicated input times | |
| Number of I/O lines | 84 |
| Number of terminals | 100 |
| Maximum operating temperature | 85 °C |
| Minimum operating temperature | -40 °C |
| organize | 0 DEDICATED INPUTS, 84 I/O |
| Output function | MACROCELL |
| Package body material | PLASTIC/EPOXY |
| encapsulated code | BGA |
| Package shape | SQUARE |
| Package form | GRID ARRAY |
| Peak Reflow Temperature (Celsius) | NOT SPECIFIED |
| Programmable logic type | EE PLD |
| propagation delay | 4.5 ns |
| Certification status | Not Qualified |
| Maximum supply voltage | 3.6 V |
| Minimum supply voltage | 3 V |
| Nominal supply voltage | 3.3 V |
| surface mount | YES |
| technology | CMOS |
| Temperature level | INDUSTRIAL |
| Terminal surface | TIN LEAD |
| Terminal form | BALL |
| Terminal location | BOTTOM |
| Maximum time at peak reflow temperature | NOT SPECIFIED |
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