White Electronic Designs
256Kx8 Monolithic SRAM
FEATURES
Access Times of 20, 25, 35, 45, 55ns
Data Retention Function (LPA Versions)
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
Organized as 256Kx8
Commercial, Industrial and Military Temperature
Ranges
JEDEC Approved Evolutionary Pinout
• 32 pin Ceramic DIP, 0.6 mils wide (Package 9)
Single +5V (±10%) Supply Operation
EDI88257CA
The EDI88257CA is a 2 Megabit 256Kx8 bit Monolithic
CMOS Static RAM.
The 32 pin DIP pinout adheres to the JEDEC evolutionary
standard for the two megabit device. The device is
upgradeable to the 512Kx8 SRAM, the EDI88512CA. Pin
1 becomes the higher order address.
A Low Power version, EDI88257LPA, offers a data retention
function for battery back-up opperation. Military product is
available compliant to Appendix A of MIL-PRF-38535.
This product is subject to change without notice.
FIGURE 1 – PIN CONFIGURATION
32 DIP
PIN DESCRIPTION
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
A17
WE#
A13
A8
A9
A11#
OE
A10
CS#
I/O7
I/O6
I/O5
I/O4
I/O3
TOP VIEW
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
I/O0-7
A0-17
WE#
CS#
OE#
V
CC
V
SS
NC
Data Inputs/Outputs
Address Inputs
Write Enable
Chip Selects
Output Enable
Power (+5V ±10%)
Ground
Not Connected
BLOCK DIAGRAM
Memory Array
A
0-17
Address
Buffer
Address
Decoder
I/O
Circuits
I/O
0-7
WE#
CS
OE#
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2000
Rev. 2
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Operating Temperature T
A
(Ambient)
Industrial
Military
Storage Temperature, Ceramic
Power Dissipation
Output Current
Junction Temperature, T
J
Value
-0.5 to 7.0
-40 to +85
-55 to +125
-65 to +150
1.5
20
175
Unit
V
°C
°C
°C
W
mA
°C
OE#
X
H
L
X
CS#
H
L
L
L
WE#
X
H
H
L
Mode
Standby
Output Deselect
Read
Write
EDI88257CA
TRUTH TABLE
Output
High Z
High Z
Data Out
Data In
Power
I
CC2
, I
CC3
I
CC1
I
CC1
I
CC1
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
4.5
0
2.2
-0.3
Typ
5.0
0
—
—
Max
5.5
0
V
CC
+0.5
+0.8
Unit
V
V
V
V
NOTE:
Stress greater than those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions greater than those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
CAPACITANCE
Parameter
Address Lines
Data Lines
Symbol
C
I
C
O
Condition
V
IN
= Vcc or Vss, f = 1.0MHz
V
OUT
= Vcc or Vss, f = 1.0MHz
Max
12
14
Unit
pF
pF
These parameters are sampled, not 100% tested.
DC CHARACTERISTICS
V
CC
= 5V, T
A
= +25°C
Parameter
Input Leakage Current
Output Leakage Current
Operating Power Supply Current
Standby (TTL) Power Supply Current
Full Standby Power Supply Current
Output Low Voltage
Output High Voltage
Symbol
I
LI
I
LO
I
CC1
I
CC2
I
CC3
V
OL
V
OH
Conditions
V
IN
= 0V to V
CC
V
I/O
= 0V to V
CC
WE#, CS# = V
IL
, I
I/O
= 0mA, Min Cycle
CS# ≥ V
IH
, V
IN
≤ V
IL
, V
IN
≥ V
IH
CS# ≥ V
CC
-0.2V
V
IN
≥ Vcc -0.2V or V
IN
≤ 0.2V
I
OL
= 8.0mA
I
OH
= -4.0mA
(20-25ns)
(35-55ns)
C
LP
Min
-10
-10
—
—
—
—
—
—
2.4
Typ
—
—
Max
+10
+10
225
200
60
25
20
0.4
—
Units
µA
µA
mA
mA
mA
mA
mA
V
V
—
—
—
—
AC TEST CONDITIONS
Figure 1
Vcc
Figure 2
Input Pulse Levels
Vcc
V
SS
to 3.0V
5ns
1.5V
Figure 1
Input Rise and Fall Times
Input and Output Timing Levels
480Ω
480Ω
Output Load
Q
255Ω
30pF
Q
255Ω
5pF
NOTE: For t
EHQZ
, t
GHQZ
and t
WLQZ
, CL = 5pF Figure 2
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2000
Rev. 2
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
AC CHARACTERISTICS – READ CYCLE
V
CC
= 5.0V, Vss = 0V, -55°C
≤
T
A
≤
+125°C
20ns
Min
20
Max
20
20
3
0
0
0
0
8
10
8
0
0
3
0
0
Min
25
25ns
Max
25
25
10
12
10
0
0
3
0
0
Min
35
Symbol
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Chip Enable to Output in Low Z (1)
Chip Disable to Output in High Z (1)
Output Hold from Address Change
Output Enable to Output Valid
Output Enable to Output in Low Z (1)
Output Disable to Output in High Z(1)
JEDEC
t
AVAV
t
AVQV
t
ELQV
t
ELQX
t
EHQZ
t
AVQX
t
GLQV
t
GLQX
t
GHQZ
Alt.
t
RC
t
AA
t
ACS
t
CLZ
t
CHZ
t
OH
t
OE
t
OLZ
t
OHZ
35ns
Max
35
35
15
15
15
0
0
3
0
0
Min
45
45ns
EDI88257CA
55ns
Min
55
Max
55
55
3
0
0
0
0
20
25
20
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Max
45
45
20
25
20
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS – WRITE CYCLE
V
CC
= 5.0V, V
SS
= 0V, -55°C≤ T
A
≤
+125°C
20ns
Min
20
15
15
0
0
15
15
15
15
0
0
0
0
0
10
10
0
Max
Min
25
17
17
0
0
17
17
17
17
0
0
0
0
0
12
12
0
25ns
Max
Min
35
25
25
0
0
25
25
25
25
0
0
0
0
0
20
20
0
Symbol
Parameter
Write Cycle Time
Chip Enable to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Data Hold Time
Write to Output in High Z (1)
Data to Write Time
Output Active from End of Write (1)
JEDEC
t
AVAV
t
ELWH
t
ELEH
t
AVWL
t
AVEL
t
AVWH
t
AVEH
t
WLWH
t
WLEH
t
WHAX
t
EHAX
t
WHDX
t
EHDX
t
WLQZ
t
DVWH
t
DVEH
t
WHQX
Alt.
t
WC
t
CW
t
CW
t
AS
t
AS
t
AW
t
AW
t
WP
t
WP
t
WR
t
WR
t
DH
t
DH
t
WHZ
t
DW
t
DW
t
WLZ
35ns
Max
Min
45
30
30
0
0
30
30
30
30
0
0
0
0
0
25
25
0
45ns
Max
Min
55
30
30
0
0
30
30
30
30
0
0
0
0
0
25
25
0
55ns
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
30
25
30
30
1. This parameter is guaranteed by design but not tested.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2000
Rev. 2
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
FIGURE 2 – TIMING WAVEFORM - READ CYCLE
t
AVAV
ADDRESS
EDI88257CA
t
AVQV
CS#
t
AVAV
ADDRESS
ADDRESS 1
ADDRESS 2
t
ELQV
t
ELQX
OE#
t
EHQZ
t
AVQV
DATA I/O
t
AVQX
DATA 1
DATA 2
t
GLQV
t
GLQX
DATA OUT
t
GHQZ
READ CYCLE 1 (WE# HIGH; OE#, CS# LOW)
READ CYCLE 2 (WE# HIGH)
FIGURE 3 – WRITE CYCLE - WE# CONTROLLED
t
AVAV
ADDRESS
t
AVWH
t
ELWH
CS#
t
WHAX
t
AVWL
WE#
t
WLWH
t
DVWH
t
WHDX
DATA IN
DATA VALID
t
WLQZ
DATA OUT
HIGH Z
t
WHQX
WRITE CYCLE 1, WE# CONTROLLED
FIGURE 4 – WRITE CYCLE - CS# CONTROLLED
t
AVAV
ADDRESS
t
AVEH
t
ELEH
CS#
t
EHAX
t
AVEL
WE#
t
WLEH
t
DVEH
t
EHDX
DATA IN
DATA OUT
HIGH Z
DATA VALID
WRITE CYCLE 2, CS# CONTROLLED
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2000
Rev. 2
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
DATA RETENTION CHARACTERISTICS (EDI88512LP ONLY)
-55°C
≤
T
A
≤
+125°C
Characteristic
Low Power Version only
Data Retention Voltage
Data Retention Quiescent Current
Chip Disable to Data Retention Time
Operation Recovery Time
Sym
V
CC
I
CCDR
t
CDR
T
R
Conditions
V
CC
= 2.0V
CS# ≥ V
CC
-0.2V
V
IN
≥ V
CC
-0.2V
or V
IN
≤ 0.2V
Min
2
–
0
t
AVAV
Typ
–
–
–
–
EDI88257CA
Max
–
2
–
–
Units
V
µA
ns
ns
FIGURE 5 – DATA RETENTION - CS# CONTROLLED
DATA RETENTION MODE
V
CC
t
CDR
CS#
CS# = V
CC
-0.2V
4.5V
V
CC
4.5V
t
R
DATA RETENTION, CS# CONTROLLED
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2000
Rev. 2
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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