GCIXF440AC datasheet, PDF - EEWORLD Datasheet

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GCIXF440AC: DescriptionLAN Controller, 8 Channel(s), 12.5MBps, CMOS, PBGA352, BGA-352; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，98 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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GCIXF440AC Overview

LAN Controller, 8 Channel(s), 12.5MBps, CMOS, PBGA352, BGA-352

GCIXF440AC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Intel
Parts packaging code	BGA
package instruction	LBGA,
Contacts	352
Reach Compliance Code	compliant
Address bus width	10
boundary scan	YES
maximum clock frequency	25 MHz
Maximum data transfer rate	12.5 MBps
External data bus width	8
JESD-30 code	S-PBGA-B352
length	35 mm
low power mode	NO
Number of serial I/Os	8
Number of terminals	352
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.67 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	35 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, LAN

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Intel

IXF440 Multiport 10/100 Mbps

Ethernet Controller

Datasheet

Product Features

The Intel

IXF440 Multiport 10/100 Mbps Ethernet Controller provides eight

10/100 Mbps intelligent, high-performance MAC ports. It includes network

management support and is optimized for switch applications.

Integration

— Eight Ethernet 10/100 Mbps MAC ports

— Onchip scrambler, descrambler, and PCS

functions for 100BASE-X connection

— Handles SNMP and RMON counters

Operation

— Enables independent 10 or 100 Mbps port

operation

— Provides full-duplex support

— Enables standard flow-control functionality in

full-duplex mode

— Offers backpressure logic capability in

half-duplex mode

— Interfaces to standard MII connections

— Supports 10BASE-T, 100BASE-TX,

100BASE-T4, and 100BASE-FX connections

— Provides programmable CRC generation and

removal

— Allows backoff limit programming

— Provides full collision support, including

jamming, backoff, and automatic

retransmission

— Complies with IEEE 802.3 Standard

IX Bus

— Supports a 4 Gbps high bus bandwidth

— Variable bus speed of 25 to 66 MHz

operational, and from 16 MHz for testing

— Interfaces a 64-bit bus with a 32-bit optional

mode

— Supports concurrent unidirectional 32-bit

buses for transmit and receive in split IX Bus

mode

— Provides transmit- and receive-independent

256-byte FIFOs for each of the eight ports

— Offers a generic slave FIFO interface

— Supports little or big endian byte ordering

— Supports transmit and receive byte alignment

— Supports receive packet fragmentation on byte

boundaries (replay feature)

— Provides programmable transmit and receive

bus thresholds

— Appends packet status to received packet

CPU Interface

— Supports fully programmable independent

ports through a dedicated generic CPU port

— Enables interrupt programming

Device

— Optimized for switch, bridge, and router

applications

— Includes internal and external loopback

capabilities

— Provides software reset support

— Supports JTAG boundary scan

— Low-power 3.3 V and 5 V tolerant CMOS

device

— 352-BGA package

Performance

— Allows status register access without

interrupting packet transfer

— Enables early address filtering ability, with

packet header preprocessing and VLAN

detection ability

— Offers retry or ignore options following

packet transmission errors

— Supports automatic retransmission following

excessive collisions

— Provides programmable automatic discard of

badly received packets such as runts, CRC

errors, and too long packets

Notice:

This document contains preliminary information on new products in production. The

specifications are subject to change without notice. Verify with your local Intel sales office that

you have the latest datasheet before finalizing a design.

Order Number: 278160-007

October, 2001

Intel

IXF440 Multiport 10/100 Mbps Ethernet Controller

Revision History

Date

11/98

3/3/00

4/24/00

5/25/00

9/26/00

5/18/01

10/02/01

Revision

001

002

003

004

005

006

007

First Intel version.

First update.

Device name change to IXF440. Describe operation in various IX Bus modes.

Changed to Intel branding.

Updates for v1.1 release of IXP1200 software.

Updates for the v1.3 SDK.

Changes to Table 22, Table 24, Section 9.0, Figure 34.

Description

Information in this document is provided in connection with Intel

products. No license, express or implied, by estoppel or otherwise, to any intellectual

property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability

whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to

fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not

intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The IXF440 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current

characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling

1-800-548-4725 or by visiting Intel's website at http://www.intel.com.

Intel is a registered trademark of Intel Corporation or its subsidiaries in the United States and other countries

*Other names and brands may be claimed as the property of others.

Datasheet

Intel

IXF440 Multiport 10/100 Mbps Ethernet Controller

Contents

1.0

Introduction......................................................................................................................... 9

1.1

1.2

2.0

2.1

2.2

2.3

2.4

3.0

3.1

3.2

General Description............................................................................................... 9

Block Diagram ....................................................................................................... 9

Signal Descriptions..............................................................................................11

Pin Count.............................................................................................................16

Connection Rules ................................................................................................16

Pin List.................................................................................................................17

3.1.1 Access Rules..........................................................................................21

CSR Register ......................................................................................................22

3.2.1 Register Mapping ...................................................................................22

3.2.2 Base Registers .......................................................................................23

3.2.2.1 Chip Interrupt Summary Register ..............................................23

3.2.2.2 Interrupt Status Register ...........................................................24

3.2.2.3 Interrupt Enable Register ..........................................................25

3.2.2.4 Transmit Status Register ...........................................................26

3.2.2.5 Receive Status Register ............................................................27

3.2.2.6 Port Control Register .................................................................28

3.2.2.7 Device ID Register ....................................................................29

3.2.2.8 Revision ID Register..................................................................29

3.2.2.9 Serial Command Register .........................................................30

3.2.3 Configuration Registers..........................................................................31

3.2.3.1 FIFO Threshold Register ...........................................................31

3.2.3.2 IX Bus Mode Register ...............................................................32

3.2.3.3 Transmit Parameters Register ..................................................33

3.2.3.4 Transmit Error Mode Register ...................................................34

3.2.3.5 Transmit Threshold and Backoff Register .................................35

3.2.3.6 Receive Parameters Register ...................................................36

3.2.3.7 Receive Filtering Mode Register ...............................................37

3.2.3.8 Transmit Pause Time Register ..................................................38

3.2.3.9 Maximum Packet Size Register ................................................38

3.2.3.10InterPacket Gap Register ..........................................................39

3.2.4 Serial Registers ......................................................................................40

3.2.4.1 Serial Mode Register .................................................................40

3.2.4.2 Link Status Register ..................................................................41

3.2.4.3 Physical Address Register ........................................................41

Network Statistic Counter Mapping .....................................................................42

3.3.1 Register Mapping ...................................................................................42

3.3.2 Network Statistic Counters Access Rules ..............................................44

Access Sequences..............................................................................................44

3.4.1 Initialization Sequence ...........................................................................44

3.4.2 Mode Change Sequence........................................................................44

3.4.3 Interrupt Handling Sequence..................................................................45

Pinout ...............................................................................................................................11

Register Descriptions .......................................................................................................21

3.3

3.4

Datasheet

iii

Intel

IXF440 Multiport 10/100 Mbps Ethernet Controller

4.0

FIFO Interface Operation ................................................................................................. 47

4.1

FIFO Interface ..................................................................................................... 47

4.1.1

Byte Ordering on IX Bus ....................................................................... 47

4.1.2 FIFO Status Signaling ............................................................................ 48

Packet Transmission........................................................................................... 48

4.2.1 Packet Loading ...................................................................................... 48

4.2.2 Network Transmission............................................................................ 49

4.2.3 Excessive Collisions............................................................................... 49

4.2.4 Late Collision.......................................................................................... 49

4.2.5 FIFO Underflow ...................................................................................... 49

4.2.6 Stopping Mode on Transmission Errors ................................................. 50

4.2.7 Transmit Flow Diagram .......................................................................... 51

Packet Reception ................................................................................................ 51

4.3.1 Packet Storing........................................................................................ 52

4.3.2 Header Preprocessing ........................................................................... 53

4.3.3 Packet Segmentation ............................................................................. 53

4.3.4 Packet Abortion ...................................................................................... 53

4.3.5 Network Reception................................................................................. 54

4.3.6 Rejecting Mode on Reception Errors ..................................................... 54

4.3.7 Accepting Mode on Reception Errors..................................................... 54

4.3.8 Receive Flow Diagram ........................................................................... 55

CPU Interface...................................................................................................... 57

Network Management ......................................................................................... 57

5.2.1 SNMP MIB Support................................................................................ 58

5.2.2 RMON Statistic Group Support .............................................................. 59

5.2.3 RMON Host Group Support ................................................................... 60

Operating Modes................................................................................................. 61

MII Port Interface................................................................................................. 62

MAC Frame Format ............................................................................................ 63

MAC Transmit Operation .................................................................................... 64

6.4.1 Transmit Initiation ................................................................................... 64

6.4.2 Initial Deferral ......................................................................................... 64

6.4.3 Frame Encapsulation ............................................................................. 64

6.4.4 Collision.................................................................................................. 65

6.4.5 Terminating Transmission ...................................................................... 65

6.4.6 Backpressure ......................................................................................... 66

6.4.7 Flow Control ........................................................................................... 66

MAC Receive Operation ..................................................................................... 66

6.5.1 Receive Initiation .................................................................................... 66

6.5.2 Preamble Processing ............................................................................. 67

6.5.3 Frame Decapsulation ............................................................................. 67

6.5.4 Terminating Reception ........................................................................... 67

6.5.5 Flow Control ........................................................................................... 68

MAC Full-Duplex Operation ................................................................................ 68

MAC Loopback Operations ................................................................................. 68

6.7.1 Internal Loopback Mode......................................................................... 68

4.2

4.3

5.0

CPU Interface Operation.................................................................................................. 57

5.1

5.2

6.0

Network Interface Operation ............................................................................................ 61

6.1

6.2

6.3

6.4

6.5

6.6

6.7

Datasheet

Intel

IXF440 Multiport 10/100 Mbps Ethernet Controller

6.8

7.0

7.1

6.7.2 External Loopback Mode........................................................................69

SYM Mode...........................................................................................................69

IX Bus Port Timing Diagrams ..............................................................................71

7.1.1 Transmit Start-of-Packet Timing.............................................................71

7.1.2 Transmit End-of-Packet Timing..............................................................72

7.1.3 Transmit FIFO Control Timing................................................................72

7.1.4 Transmit Ready (txrdy) Timing ...............................................................73

7.1.5 Receive Start-of-Packet Timing..............................................................73

7.1.6 Receive End-of-Packet Timing...............................................................74

7.1.7 Fastest Receive Reaccess after EOP ....................................................74

7.1.8 Receive rxfail Timing ..............................................................................75

7.1.9 Receive rxabt Timing..............................................................................75

7.1.10 Receive rxkep Timing.............................................................................76

7.1.11 Receive Header Replay Timing..............................................................76

7.1.12 Receive FIFO Control Timing.................................................................76

7.1.13 Receive Ready (rxrdy) Control Timing ...................................................77

7.1.14 Consecutive Transmit-Transmit Timing..................................................77

7.1.15 Consecutive Transmit-Receive Timing...................................................78

7.1.16 Consecutive Receive-Transmit Timing...................................................78

7.1.17 Consecutive Receive-Receive Timing....................................................78

MII/SYM Port Timing Diagrams...........................................................................78

7.2.1 Packet Transmission Timing ..................................................................79

7.2.2 Packet Reception Timing .......................................................................79

7.2.3 Transmission with Collision Timing ........................................................79

7.2.4 False Carrier Timing...............................................................................79

Functional Operating Range ...............................................................................81

Absolute Maximum Rating ..................................................................................81

Supply Current and Power Dissipation................................................................82

Temperature Limit Ratings ..................................................................................82

Reset Specification..............................................................................................82

FIFO Port Specifications .....................................................................................83

8.6.1 Clock Specification .................................................................................83

8.6.2 3.3 Volt DC Specifications......................................................................83

8.6.3 5 Volt DC Specifications.........................................................................84

8.6.4 IX Bus Signals Timing ............................................................................84

CPU Port Specifications ......................................................................................85

8.7.1 DC Specifications ...................................................................................85

8.7.2 Signals Timing........................................................................................85

8.7.2.1 Read Timing ..............................................................................85

8.7.2.2 Write Timing ..............................................................................86

8.7.2.3 Timing Parameters ....................................................................87

MII/SYM Port Specifications................................................................................87

8.8.1 DC Specifications ...................................................................................87

8.8.2 Signals Timing........................................................................................87

8.8.2.1 Clocks Specifications ................................................................88

8.8.2.2 Signals Timing Diagrams ..........................................................88

8.8.2.3 Data Timing Parameters ...........................................................89

Timing Diagrams ..............................................................................................................71

7.2

8.0

Electrical and Environmental Specifications.....................................................................81

8.1

8.2

8.3

8.4

8.5

8.6

8.7

8.8

Datasheet

GCIXF440AC Related Products

	GCIXF440AC	GCIXF440ACT
Description	LAN Controller, 8 Channel(s), 12.5MBps, CMOS, PBGA352, BGA-352	LAN Controller, 8 Channel(s), 12.5MBps, CMOS, PBGA352, BGA-352
Is it Rohs certified?	incompatible	incompatible
Maker	Intel	Intel
Parts packaging code	BGA	BGA
package instruction	LBGA,	LBGA,
Contacts	352	352
Reach Compliance Code	compliant	compliant
Address bus width	10	10
boundary scan	YES	YES
maximum clock frequency	25 MHz	66.66 MHz
Maximum data transfer rate	12.5 MBps	12.5 MBps
External data bus width	8	8
JESD-30 code	S-PBGA-B352	S-PBGA-B352
length	35 mm	35 mm
low power mode	NO	NO
Number of serial I/Os	8	8
Number of terminals	352	352
Maximum operating temperature	70 °C	85 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LBGA	LBGA
Package shape	SQUARE	SQUARE
Package form	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.67 mm	1.67 mm
Maximum supply voltage	3.6 V	3.6 V
Minimum supply voltage	3 V	3 V
Nominal supply voltage	3.3 V	3.3 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	COMMERCIAL	INDUSTRIAL
Terminal form	BALL	BALL
Terminal pitch	1.27 mm	1.27 mm
Terminal location	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
width	35 mm	35 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, LAN	SERIAL IO/COMMUNICATION CONTROLLER, LAN

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