M27C516
512 Kbit (32Kb x16) OTP EPROM
5V
±
10% SUPPLY VOLTAGE in READ
OPERATION
FAST ACCESS TIME: 35ns
LOW POWER CONSUMPTION:
– Active Current 30mA at 5MHz
– Stand-by Current 100µA
PROGRAMMING VOLTAGE: 12.75V
±
0.25V
PROGRAMMING TIME: 100
µ
s/word (typical)
ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Device Code: 000Fh
PLCC44 (C)
TSOP40 (N)
10 x 14mm
Figure 1. Logic Diagram
DESCRIPTION
The M27C516 is a 512 Kbit EPROM offered in the
OTP range (one time programmable). It is ideally
suited for microprocessor systems requiring large
data or program storage and is organized as
32,768 words of 16 bits.
The M27C516 is offered in a PLCC44 and TSOP40
(10 x 14mm) packages.
15
A0-A14
VCC
VPP
16
Q0-Q15
P
Table 1. Signal Names
A0-A14
Q0-Q15
E
G
P
V
CC
V
PP
V
SS
Address Inputs
Data Outputs
Chip Enable
Output Enable
Program Enable
Supply Voltage
Program Supply
Ground
M27C516
E
G
VSS
AI00932
September 1998
1/12
M27C516
Figure 2A. LCC Pin Connections
Figure 2B. TSOP Pin Connections
A9
A10
A11
A12
A13
A14
NC
NC
P
VCC
VPP
E
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
1
40
VSS
A8
A7
A6
A5
A4
A3
A2
A1
A0
G
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VSS
Q12
Q11
Q10
Q9
Q8
VSS
NC
Q7
Q6
Q5
Q4
Q13
Q14
Q15
E
VPP
NC
VCC
P
NC
NC
A14
1 44
A13
A12
A11
A10
A9
VSS
NC
A8
A7
A6
A5
12
M27C516
34
10
11
M27C516
(Normal)
31
30
23
Q3
Q2
Q1
Q0
G
NC
A0
A1
A2
A3
A4
AI00934
20
21
AI01600
Warning:
NC = Not Connected.
Warning:
NC = Not Connected.
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
BIAS
T
STG
V
IO
(2)
Parameter
Ambient Operating Temperature
(3)
Temperature Under Bias
Storage Temperature
Input or Output Voltages (except A9)
Supply Voltage
A9 Voltage
Program Supply Voltage
Value
–40 to 125
–50 to 125
–65 to 150
–2 to 7
–2 to 7
–2 to 13.5
–2 to 14
Unit
°
C
°C
°
C
V
V
V
V
V
CC
V
A9 (2)
V
PP
Notes:
1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not i mplied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
CC
+0.5V with possible overshoot to V
CC
+2V for a period less than 20ns.
3. Depends on range.
2/12
M27C516
Table 3. Operating Modes
Mode
Read
Output Disable
Program
Verify
Program Inhibit
Standby
Electronic Signature
Notes
: X = V
IH
or V
IL
, V
ID
= 12V
±
0.5V
E
V
IL
V
IL
V
IL
V
IL
V
IH
V
IH
V
IL
G
V
IL
V
IH
X
V
IL
X
X
V
IL
P
V
IH
X
V
IL
Pulse
V
IH
X
X
V
IH
A9
X
X
X
X
X
X
V
ID
V
PP
V
CC
V
CC
V
PP
V
PP
V
PP
V
CC
V
CC
Q0 - Q15
Data Out
Hi-Z
Data In
Data Out
Hi-Z
Hi-Z
Codes
Table 4. Electronic Signature
Identifier
Manufacturer’s Code
Device Code
A0
V
IL
V
IH
Q7
0
0
Q6
0
0
Q5
1
0
Q4
0
0
Q3
0
1
Q2
0
1
Q1
0
1
Q0
0
1
Hex Data
20h
0Fh
Note:
Outputs Q8-Q15 are set to ’0’.
DEVICE OPERATION
The operating modes of the M27C516 are listed in
the Operating Modes table. A single power supply
is required in the read mode. All inputs are TTL
levels except for G and 12V on A9 for Electronic
Signature.
Read Mode
The M27C516 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, inde-
pendent of device selection. Assuming that the
addresses are stable, the address access time
(t
AVQV
) isequal to the delay from E to output(t
ELQV
).
Data is available at the output after a delay of t
GLQV
from the falling edge of G, assuming that E has
been low and the addresses have been stable for
at least t
AVQV
-t
GLQV
.
Standby Mode
The M27C516 has a standby mode which reduces
the supply current from 30mA to 100µA. The
M27C516 is placed in the standby mode by apply-
ing a CMOS high signal to the E input. When in the
standbymode, the outputs are in a high impedance
state, independent of the G input.
Two Line Output Control
Because OTP EPROMs are usually used in larger
memory arrays, the product featuresa 2 line control
function which accommodates the use of multiple
memory connection. The two line control function
allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficientuse of these two control lines,
E should be decoded and used as the primary
device selecting function, while G should be made
a common connection to all devices in the array
and connected to the READ line from the system
control bus. This ensures that all deselected mem-
ory devices are in their low power standby mode
and that the output pins are only active when data
is required from a particular memory device.
3/12
M27C516
Table 5. AC Measurement Conditions
High Speed
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
≤
10ns
0 to 3V
1.5V
Standard
≤
20ns (10% to 90%)
0.4V to 2.4V
0.8V and 2V
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
High Speed
3V
1.5V
0V
3.3kΩ
DEVICE
UNDER
TEST
1N914
Standard
2.4V
2.0V
0.8V
AI01822
OUT
CL = 30pF or 60pF or 100pF
0.4V
CL includes JIG capacitance
AI02024B
Table 6. Capacitance
(T
A
= 25
°
C, f = 1 MHz )
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Test Condition
V
IN
= 0V
V
OUT
= 0V
Min
Max
6
12
Unit
pF
pF
Notes.
1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously with or after V
PP
.
2. This parameter is sampled only and not tested 100%.
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, I
CC
, has three seg-
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
the transient current peaks is dependent on the
capacitiveand inductiveloading of thedevice at the
output. The associated transient voltagepeaks can
be suppressed by complying with the two line
output control and by properlyselected decoupling
capacitors. It is recommended that a 1µF ceramic
capacitor be used on every device between V
CC
and V
SS
. This should be a high frequencycapacitor
of low inherent inductance and should be placed
as close to the device as possible. In addition, a
4.7µF bulk electrolytic capacitor should be used
between V
CC
and V
SS
for every eight devices. The
bulk capacitor should be located near the power
supplyconnection point.The purpose of the bulk
capacitor is to overcome the voltage drop caused
by the inductive effects of PCB traces.
4/12
M27C516
Table 7. Read Mode DC Characteristics
(1)
(T
A
= 0 to 70
°C
or –40 to 85
°C;
V
CC
= 5V
±
5% or 5V
±
10%; V
PP
= V
CC
)
Symbol
I
LI
I
LO
I
CC
I
CC1
I
CC2
I
PP
V
IL
V
IH (2)
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Supply Current
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage TTL
Output High Voltage CMOS
I
OL
= 2.1mA
I
OH
= –400µA
I
OH
= –100µA
2.4
V
CC
–0.7V
Test Condition
0V
≤
V
IN
≤
V
CC
0V
≤
V
OUT
≤
V
CC
E = V
IL
, G = V
IL
, f = 5MHz
E = V
IH
E > V
CC
– 0.3V
V
PP
= V
CC
–0.3
2
Min
Max
±
1
±5
30
1
100
10
0.8
V
CC
+ 1
0.4
Unit
µ
A
µA
mA
mA
µ
A
µA
V
V
V
V
V
Notes:
1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Maximum DC Voltage on Output is V
CC
+0.5V.
Table 8A. Read Mode AC Characteristics
(1)
(T
A
= 0 to 70
°C
or –40 to 85
°C;
V
CC
= 5V
±
5% or 5V
±
10%; V
PP
= V
CC
)
M27C516
Symbol
Alt
Parameter
Test Condition
-35
(3)
Min
t
AVQV
t
ELQV
t
GLQV
t
EHQZ (2)
t
GHQZ (2)
t
AXQX
Notes:
1.
2.
3.
4.
-45
(3)
Min
Max
45
45
23
0
0
0
18
18
0
0
0
-55
(4)
Min
Max
55
55
25
20
20
Unit
Max
35
35
18
t
ACC
t
CE
t
OE
t
DF
t
DF
t
OH
Address Valid to Output
Valid
Chip Enable Low to
Output Valid
Output Enable Low to
Output Valid
Chip Enable High to
Output Hi-Z
Output Enable High to
Output Hi-Z
Address Transition to
Output Transition
E = V
IL
, G = V
IL
G = V
IL
E = V
IL
G = V
IL
E = V
IL
E = V
IL
, G = V
IL
0
0
0
ns
ns
ns
ns
ns
ns
18
18
V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously with or after V
PP.
Sampled only, not 100% tested.
Speed obtained with High Speed measurement conditions and a load capacitance of 30pF.
Speed obtained with a load capacitance of 60pF.
5/12
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