IDT70V07S35PF9 datasheet, PDF - EEWORLD Datasheet

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IDT70V07S35PF9: DescriptionDual-Port SRAM, 32KX8, 35ns, CMOS, PQFP80, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-80; Categorystorage storage; File Size163KB，18 Pages; ManufacturerIDT (Integrated Device Technology)

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IDT70V07S35PF9 Overview

Dual-Port SRAM, 32KX8, 35ns, CMOS, PQFP80, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-80

IDT70V07S35PF9 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	14 X 14 MM, 1.40 MM HEIGHT, TQFP-80
Contacts	80
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	35 ns
Other features	INTERRUPT FLAG; SEMAPHORE; AUTOMATIC POWER-DOWN
JESD-30 code	S-PQFP-G80
JESD-609 code	e0
length	14 mm
memory density	262144 bit
Memory IC Type	DUAL-PORT SRAM
memory width	8
Humidity sensitivity level	3
Number of functions	1
Number of ports	2
Number of terminals	80
word count	32768 words
character code	32000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	32KX8
Output characteristics	3-STATE
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	20
width	14 mm

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HIGH-SPEED 3.3V

32K x 8 DUAL-PORT

STATIC RAM

Features

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

High-speed access

– Commercial: 25/35/55ns (max.)

– Industral: 25ns (max.)

Low-power operation

– IDT70V07S

Active: 300mW (typ.)

Standby: 3.3mW (typ.)

– IDT70V07L

Active: 300mW (typ.)

Standby: 660

W (typ.)

Interrupt Flag

IDT70V07S/L

◆

IDT70V07 easily expands data bus width to 16 bits or more

using the Master/Slave select when cascading more than

one device

M/S = V

for

BUSY

output flag on Master

M/S = V

for

BUSY

input on Slave

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

TTL-compatible, single 3.3V (±0.3V) power supply

Available in 68-pin PGA and PLCC, and a 80-pin TQFP

Industrial temperature range (-40°C to +85°C) is available

for selected speeds

Functional Block Diagram

R/W

I/O

- I/O

I/O

Control

BUSY

14L

(1,2)

I/O

Control

I/O

-I/O

BUSY

Address

Decoder

(1,2)

MEMORY

ARRAY

Address

Decoder

14R

R/W

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

R/W

SEM

(2)

INT

M/S

SEM

INT

R(2)

2943 drw 01

NOTES:

1. (MASTER):

BUSY

is output; (SLAVE):

BUSY

is input.

BUSY

and

INT

outputs are non-tri-stated push-pull.

OCTOBER 2004

DSC 2943/6

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