Preliminary
GS8182S08/09/18BD-333/300/250/200/167
165-Bump BGA
Commercial Temp
Industrial Temp
Features
• Simultaneous Read and Write SigmaSIO™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• DLL circuitry for wide output data valid window and future
frequency scaling
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ mode pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with present 9Mb, 36Mb, and 72Mb and
future 144Mb devices
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
18Mb Burst of 2
DDR SigmaSIO-II SRAM
333 MHz–167 MHz
1.8 V V
DD
1.8 V and 1.5 V I/O
Bottom View
165-Bump, 13 mm x 15 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
JEDEC Std. MO-216, Variation CAB-1
SigmaRAM™ Family Overview
GS8182S08/09/18 are built in compliance with the SigmaSIO-
II SRAM pinout standard for Separate I/O synchronous
SRAMs. They are 16,777,216-bit (18Mb) SRAMs. These are
the first in a family of wide, very low voltage HSTL I/O
SRAMs designed to operate at the speeds needed to implement
economical high performance networking systems.
inputs, C and C. If the C clocks are tied high, the K clocks are
routed internally to fire the output registers instead. Each Burst
of 2 SigmaSIO-II SRAM also supplies Echo Clock outputs,
CQ and CQ, which are synchronized with read data output.
When used in a source synchronous clocking scheme, the Echo
Clock outputs can be used to fire input registers at the data’s
destination.
Because Separate I/O Burst of 2 RAMs always transfer data in
two packets, A0 is internally set to 0 for the first read or write
transfer, and automatically incremented by 1 for the next
transfer. Because the LSB is tied off internally, the address
field of a Burst of 2 RAM is always one address pin less than
the advertised index depth (e.g., the 1M x 18 has a 512K
addressable index).
Clocking and Addressing Schemes
A Burst of 2 SigmaSIO-II SRAM is a synchronous device. It
employs dual input register clock inputs, K and K. The device
also allows the user to manipulate the output register clock
input quasi independently with dual output register clock
Parameter Synopsis
- 333
tKHKH
tKHQV
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
-250
4.0 ns
0.45 ns
-200
5.0 ns
0.45 ns
-167
6.0 ns
0.5 ns
Rev: 1.00a 6/2007
1/36
© 2007, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8182S08/09/18BD-333/300/250/200/167
Pin Description Table
Symbol
SA
NC
R/W
NW0–NW1
BW
BW0–BW1
K
C
TMS
TDI
TCK
TDO
V
REF
ZQ
K
C
D
OFF
LD
CQ
CQ
Dn
Qn
V
DD
V
DDQ
V
SS
Description
Synchronous Address Inputs
No Connect
Read/Write Contol Pin
Synchronous Nybble Writes
Synchronous Byte Writes
Synchronous Byte Writes
Input Clock
Output Clock
Test Mode Select
Test Data Input
Test Clock Input
Test Data Output
HSTL Input Reference Voltage
Output Impedance Matching Input
Input Clock
Output Clock
DLL Disable
Synchronous Load Pin
Output Echo Clock
Output Echo Clock
Synchronous Data Inputs
Synchronous Data Outputs
Power Supply
Isolated Output Buffer Supply
Power Supply: Ground
Type
Input
—
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
Input
Output
—
—
Output
Output
Input
Output
Supply
Supply
Supply
Comments
—
—
Write Active Low; Read Active High
Active Low
x08 Version
Active Low
x09 Version
Active Low
x18 Version
Active High
Active High
—
—
—
—
—
—
Active Low
Active Low
Active Low
Active Low
Active Low
Active High
1.8 V Nominal
1.8 or 1.5 V Nominal
—
Notes:
1. C, C, K, or K cannot be set to V
REF
voltage.
2. When ZQ pin is directly connected to V
DD
, output impedance is set to minimum value and it cannot be connected to ground or left
unconnected.
3. NC = Not Connected to die or any other pin
Rev: 1.00a 6/2007
5/36
© 2007, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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