A416316B Series
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Features
Organization: 65,536 words X 16 bits
Part Identification:
-
A416316B
-
A416316B-L (with self-refresh mode)
High speed
- 30/35/40 ns
RAS access time
- 16/18/20 ns column address access time
- 10/11/12 ns CAS access time
Low power consumption
- Operating: 75mA (-30 max)
-
Standby: 3 mA (TTL)
Separate CAS (
UCAS
,
LCAS
) for byte selection
Self refresh mode
256 refresh cycles, 4 ms refresh interval
Read-modify-write, RAS -only, CAS -before- RAS ,
Hidden refresh capability
TTL-compatible, three-state I/O
JEDEC standard packages
-
400mil, 40-pin SOJ
-
400mil, 40/44 TSOP type II package
Single 5V power supply/built-in VBB generator
Pin Configuration
SOJ
TSOP
Pin Descriptions
Symbol
VCC
I/O
0
I/O
1
I/O
2
I/O
3
VCC
I/O
4
I/O
5
I/O
6
I/O
7
NC
NC
WE
RAS
NC
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VSS
I/O
15
I/O
14
I/O
13
I/O
12
VSS
I/O
11
I/O
10
I/O
9
I/O
8
NC
LCAS
UCAS
OE
NC
A7
A6
A5
A4
VSS
VCC
I/O
0
I/O
1
I/O
2
I/O
3
VCC
I/O
4
I/O
5
I/O
6
I/O
7
NC
NC
WE
RAS
NC
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
32
31
30
29
28
27
26
25
24
23
VSS
I/O
15
I/O
14
I/O
13
I/O
12
VSS
I/O
11
I/O
10
I/O
9
I/O
8
NC
LCAS
UCAS
OE
NC
A7
A6
A5
A4
VSS
Description
A0 – A7
I/O
0
- I/O
15
RAS
Address Inputs
Data Input/Output
Row Address Strobe
Column Address Strobe/Upper Byte
Control
Column Address Strobe/Lower Byte
Control
Write Enable
Output Enable
+5V Power Supply
Ground
No Connection
(August, 2004, Version 1.1)
A416316BS
A416316BV
UCAS
LCAS
WE
OE
VCC
VSS
NC
1
AMIC Technology, Corp.
A416316B Series
Selection Guide
Symbol
Description
-30
-35
-40
Unit
t
RAC
t
AA
t
CAC
t
OEA
t
RC
t
PC
I
CC1
I
CC6
Maximum RAS Access Time
Maximum Column Address Access Time
Maximum CAS Access Time
Maximum Output Enable ( OE ) Access Time
Minimum Read or Write Cycle Time
Minimum Fast Page Mode Cycle Time
Maximum Operating Current
Maximum CMOS Standby Current
30
16
10
10
65
19
95
2
35
18
11
11
70
21
85
2
40
20
12
12
75
23
75
2
ns
ns
ns
ns
ns
ns
mA
mA
Functional Description
The A416316B is a high performance CMOS Dynamic
Random Access Memory organized as 65,536 words X 16
bits. The A416316B is fabricated with advanced CMOS
technology and designed with innovative design techniques
resulting in high speed, extremely low power and wide
operating margins at component and system levels.
The A416316B features a high speed page mode operation
in which high speed read, write and read-write are
performed on any of the bits defined by the column
address. The asynchronous column address uses an
extremely short row address capture time to ease the
system level timing constraints associated with multiplexed
addressing. Output is tri-stated by a column address strobe
(
UCAS
and
LCAS
) which acts as an output enable
independent of RAS . Very fast
UCAS
and
LCAS
to
output access time eases system design.
All inputs are TTL compatible. Fast Page Mode operation
allows random access up to 256 X 16 bits within a page,
with cycle time as short as 19/21/23 ns.
The A416316B is best suited for graphics, digital signal
processing and high performance peripherals.
The A416316B is available in JEDEC standard 40-pin
plastic SOJ package and 40/44 TSOP type II package.
(August, 2004, Version 1.1)
2
AMIC Technology, Corp.
A416316B Series
Truth Table
Function
RAS
H
L
L
UCAS
H
L
H
LCAS
H
L
L
WE
L
H
H
OE
L
L
L
Address
I/Os
Notes
Standby
Read: Word
Read: Lower Byte
L
Row/Col.
Row/Col.
L
Data Out
I/O
0-7
= Data Out
I/O
8-15
= High-Z
I/O
0-7
= High-Z
I/O
8-15
= Data Out
Data In
I/O
0-7
= Data In
I/O
8-15
= X
I/O
0-7
= X
I/O
8-15
= Data In
Data Out
→
Data In
Data Out
Data Out
Data In
Data In
Data In
Data In
Data Out
Data In
→
High-Z
High-Z
High-Z
High-Z
3
1.2
2
2
1
1
1, 2
1, 2
2
1
Read: Upper Byte
L
L
H
H
L
Row/Col.
Write: Word(Early)
Write: Lower Byte(Early)
L
L
L
H
L
L
L
L
X
X
Row/Col.
Row/Col.
Write: Upper Byte(Early)
L
L
H
L
H
→
L
H
H
L
L
H
→
L
H
→
L
H
L
X
X
X
X
L
→
H
H
→
L
H
→
L
X
X
L
→
H
L
→
H
L
X
X
X
X
Row/Col.
Read-Write
Fast-Page-Mode Read: Hi-Z
-First cycle
-Subsequent Cycles
Fast-Page-Mode Write(Early)
-First cycle
-Subsequent Cycles
Fast-Page-Mode Read-Write
-First cycle
-Subsequent Cycles
Hidden Refresh Read
Hidden Refresh Write
RAS -Only Refresh
CBR Refresh
Self Refresh (L-ver only)
Note:
L
L
L
L
L
L
L
L
→
H
→
L
L
→
H
→
L
L
H
→
L
H
→
L
L
H
→
L
H
→
L
H
→
L
H
→
L
H
→
L
H
→
L
L
L
H
L
L
L
H
→
L
H
→
L
H
→
L
H
→
L
H
→
L
H
→
L
L
L
H
L
L
Row/Col.
Row/Col.
Col.
Row/Col.
Col.
Row/Col.
Col.
Row/Col.
Row/Col.
Row
X
X
1. Byte Write may be executed with either
UCAS
or
LCAS
active.
2. Byte Read may be executed with either
UCAS
or
LCAS
active.
3. Only one
CAS
signal (
UCAS
or
LCAS
) must be active.
(August, 2004, Version 1.1)
4
AMIC Technology, Corp.