80186 80188
HIGH-INTEGRATION 16-BIT MICROPROCESSORS
Y
Integrated Feature Set
Enhanced 8086-2 CPU
Clock Generator
2 Independent DMA Channels
Programmable Interrupt Controller
3 Programmable 16-bit Timers
Programmable Memory and
Peripheral Chip-Select Logic
Programmable Wait State Generator
Local Bus Controller
Available in 10 MHz and 8 MHz
Versions
High-Performance Processor
4 Mbyte Sec Bus Bandwidth
Interface
8 MHz (80186)
5 Mbyte Sec Bus Bandwidth
Interface
10 MHz (80186)
Y
Direct Addressing Capability to 1 Mbyte
of Memory and 64 Kbyte I O
Completely Object Code Compatible
with All Existing 8086 8088 Software
10 New Instruction Types
Numerics Coprocessing Capability
Through 8087 Interface
Available in 68 Pin
Plastic Leaded Chip Carrier (PLCC)
Ceramic Pin Grid Array (PGA)
Ceramic Leadless Chip Carrier (LCC)
Available in EXPRESS
Standard Temperature with Burn-In
Extended Temperature Range
(
b
40 C to
a
85 C)
Y
Y
Y
Y
Y
Y
272430 –1
Figure 1 Block Diagram
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
November 1994
COPYRIGHT
INTEL CORPORATION 1995
Order Number 272430-002
1
80186 80188
Table 1 Pin Descriptions
Symbol
V
CC
V
SS
RESET
Pin
No
9
43
26
60
57
Type
I
I
O
Name and Function
SYSTEM POWER
a
5 volt power supply
System Ground
Reset Output indicates that the CPU is being reset and can be used as a system
reset It is active HIGH synchronized with the processor clock and lasts an
integer number of clock periods corresponding to the length of the RES signal
Crystal Inputs X1 and X2 provide external connections for a fundamental mode
parallel resonant crystal for the internal oscillator Instead of using a crystal an
external clock may be applied to X1 while minimizing stray capacitance on X2
The input or oscillator frequency is internally divided by two to generate the
clock signal (CLKOUT)
Clock Output provides the system with a 50% duty cycle waveform All device
pin timings are specified relative to CLKOUT
An active RES causes the processor to immediately terminate its present
activity clear the internal logic and enter a dormant state This signal may be
asynchronous to the processor clock The processor begins fetching
instructions approximately 6 clock cycles after RES is returned HIGH For
proper initialization V
CC
must be within specifications and the clock signal must
be stable for more than 4 clocks with RES held LOW RES is internally
synchronized This input is provided with a Schmitt-trigger to facilitate power-on
RES generation via an RC network
TEST is examined by the WAIT instruction If the TEST input is HIGH when
‘‘WAIT’’ execution begins instruction execution will suspend TEST will be
resampled until it goes LOW at which time execution will resume If interrupts
are enabled while the processor is waiting for TEST interrupts will be serviced
During power-up active RES is required to configure TEST as an input This pin
is synchronized internally
Timer Inputs are used either as clock or control signals depending upon the
programmed timer mode These inputs are active HIGH (or LOW-to-HIGH
transitions are counted) and internally synchronized
Timer outputs are used to provide single pulse or continous waveform
generation depending upon the timer mode selected
DMA Request is asserted HIGH by an external device when it is ready for DMA
Channel 0 or 1 to perform a transfer These signals are level-triggered and
internally synchronized
The Non-Maskable Interrupt input causes a Type 2 interrupt An NMI transition
from LOW to HIGH is latched and synchronized internally and initiates the
interrupt at the next instruction boundary NMI must be asserted for at least one
clock The Non-Maskable Interrupt cannot be avoided by programming
Maskable Interrupt Requests can be requested by activating one of these pins
When configured as inputs these pins are active HIGH Interrupt Requests are
synchronized internally INT2 and INT3 may be configured to provide active-
LOW interrupt-acknowledge output signals All interrupt inputs may be
configured to be either edge- or level-triggered To ensure recognition all
interrupt requests must remain active until the interrupt is acknowledged When
Slave Mode is selected the function of these pins changes (see Interrupt
Controller section of this data sheet)
X1
X2
59
58
I
O
CLKOUT
RES
56
24
O
I
TEST
47
I O
TMR IN 0
TMR IN 1
TMR OUT 0
TMR OUT 1
DRQ0
DRQ1
NMI
20
21
22
23
18
19
46
I
I
O
O
I
I
I
INT0
INT1 SELECT
INT2 INTA0
INT3 INTA1 IRQ
45
44
42
41
I
I
I O
I O
NOTE
Pin names in parentheses apply to the 80188
5
5
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