SP5511
Bidirectional I
2
C Bus 4-Address Synthesiser
DS3090 - 4.0 January 1997
The SP5511 is a single-chip frequency synthesiser designed
for TV tuning systems. Control data is entered in the standard
I
2
C BUS format. In 18-lead plastic DIL package, the SP5511
has three addressable current-limited output ports (P0-P3) and
four bi-directional output ports (P0-P2) and four addressable
bi-directional open-collector ports (P4-P7) of which P6 is also
a 3-bit 5-level ADC input. The information on these ports can
be read via the I
2
C BUS. The SP5511S is a variant in a 16-lead
miniature plastic package, without P0-P2 but functionally
identical in other respects to the SP5511.
The device has four programmable I
2
C BUS addresses,
allowing two or more synthesisers to be used in a system.
CHARGE PUMP
CRYSTAL Q1
CRYSTAL Q2
SDA
SCL
1
2
3
4
18
17
16
15
DRIVE OUTPUT
V
EE
RF INPUT
RF INPUT
V
CC
P0 OUTPUT PORT
P1 OUTPUT PORT
P2 OUTPUT PORT
P3 ADD SELECT PORT
5
SP5511
14
6
7
8
9
13
12
11
10
†
I/O PORT P7
FEATURES
s
Complete 1·3GHz Single Chip System
*
I/O PORT P6
†
I/O PORT P5
†
I/O PORT P4
s
s
s
s
s
s
s
s
s
s
Programmable via the I C BUS
Low Power Consumption (240mW Typ.)
Low Radiation
Phase Lock Detector
Varactor Drive Amp Disable
7 Controllable Outputs, 4 Bi-directional (SP5511)
4 Bi-directional Controllable Outputs (SP5511S)
5-Level ADC
Variable I C BUS Address for Picture in Picture TV
ESD Protection
*
2
2
DP18
CHARGE PUMP
CRYSTAL Q1
CRYSTAL Q2
SDA
SCL
1
16
DRIVE OUTPUT
V
EE
RF INPUT
RF INPUT
V
CC
NC
P3 ADD SELECT PORT
I/O PORT P4
SP5511S
†
I/O PORT P7
*
I/O PORT P6
†
I/O PORT P5
8
9
†
*
Normal ESD handling precautions should be observed.
APPLICATIONS
† = Logic level I/O port
*
= 3-bit ADC input
MP16
s
Cable Tuning Systems
s
VCRs
ORDERING INFORMATION
SP5511 NA DP
(18-lead plastic package)
SP5511S NA MP
(16-lead miniature plastic package)
Fig. 1 Pin connections – top view
SP5511
ELECTRICAL CHARACTERISTICS
T
AMB
=
210°C
to
180°C,
V
CC
=
14·5V
to
15·5V.
All pin references are to the SP5511 (DP18 package).
These Characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature
and supply voltage ranges unless otherwise stated. Reference frequency 4MHz unless otherwise stated.
Value
Characteristic
Supply current
Prescaler input voltage
Prescaler input impedance
Prescaler input capacitance
SDA, SCL
Input high voltage
Input low voltage
Input high current
Input low current
Leakage current
SDA
Output voltage
Charge pump current low
Charge pump current high
Charge pump output leakage current
Charge pump drive output current
Charge pump amplifier gain
Recommended crystal series resistance
Crystal oscillator drive level
Crystal oscillator negative resistance
Output Ports
P0-P2 sink current (see note 1)
P0-P2 leakage current (see note 1)
P4-P7 sink current
P4-P7 leakage current
Input Ports
P3 input current high
P3 input current low
P4, P5, P7 input voltage low
P4, P5, P7 input voltage high
P6 input current high
P6 input current low
Pin
Min.
14
15,16
15,16
Typ.
48
12·5
30
50
2
3
0
5·5
1·5
10
210
10
0·4
650
6170
65
500
6400
10
40
2
11-13
11-13
6-9
6-9
10
10
6,8,9
6,8,9
7
7
750
0·7
10
10
1
20·5
0·8
2·7
110
210
1
1·5
10
200
Ω
Parallel resonant crystal (note 2)
mV p-p
Ω
mA
µA
mA
µA
mA
mA
V
V
µA
µA
V
OUT
= 12V
V
OUT
= 13·2V
V
OUT
= 0·7V
V
OUT
= 13·2V
V pin 10 = 13·2V
V pin 10 = 0V
Max.
60
300
300
V
CC
= 5V
mA
mVrms 80MHz to 1GHz
mVrms 1·3GHz, see Fig. 5
Ω
pF
V
V
µA
µA
µA
V
µA
µA
nA
Units
Conditions
4,5
4,5
4,5
4,5
4,5
4
1
1
1
18
Input voltage = V
CC
Input voltage = 0V
When V
CC
= 0V
Sink current = 3mA
Byte 4, bit 2 = 0, pin 1 = 2V
Byte 4, bit 2 = 1, pin 1 = 2V
Byte 4, bit 4 = 1, pin 1 = 2V
V pin 18 = 0·7V
See Table 3 for ADC levels
NOTES
1. Ports P0-P2 not present on the SP5511S
2. The maximum resistance quoted refers to all conditions, including start-up.
2
SP5511
The SP5511 is programmed from an I
2
C BUS. Data and
Clock are fed in on the SDA and SCL lines respectively as
defined by the I
2
C Bus format. The synthesiser can either
accept new data (write mode) or send data (read mode). The
Tables in Fig. 3 illustrate the format of the data. The device
can be programmed to respond to several addresses, which
enables the use of more than one synthesiser in an I
2
C BUS
system. Table 4 shows how the address is selected by
applying a voltage to P3. The address input circuit is shown
in Fig.6.The LSB of the address Byte (R/W) sets the device
into read mode if it is high and write mode if it is low. When
the SP5511 receives a correct address Byte it pulls the SDA
line low during the acknowledge period and during following
acknowledge periods after further data Bytes are programmed.
When the SP5511 is programmed into the read mode the
controlling device accepting the data must pull down the SDA
line during the following acknowledge period to read another
status Byte.
FUNCTIONAL DESCRIPTION
WRITE MODE (FREQUENCY SYNTHESIS)
When the device is in the write mode Bytes 213 select the
synthesised frequency while Bytes 415 select the output port
states and charge pump information.
Once the correct address is received and acknowledged,
the first Bit of the next Byte determines whether that Byte is
interpreted as Byte 2 or 4, a logic 0 for frequency information
and a logic 1 for charge pump and output port information.
Additional data Bytes can be entered without the need to re-
address the device until an I
2
C stop condition is recognised.
This allows a smooth frequency sweep for fine tuning or AFC
purposes.
If the transmission of data is stopped mid-byte (i.e., by
another device on the bus) then the previously programmed
byte is maintained.
Frequency data from Bytes 2 and 3 is stored in a 15-bit shift
register and is used to control the division ratio of the 15-bit
programmable divider which is preceded by a divide-by-8
prescaler and amplifier to give excellent sensitivity at the local
oscillator input; see Fig 5. The input impedance is shown in
Figs. 7 and 8.
The programmed frequency can be calculated by multiply-
ing the programmed division ratio by 8 times the comparison
frequency F
COMP
.
When frequency data is entered, the phase comparator,
via the charge pump and varactor drive amplifier, adjusts the
local oscillator control voltage until the output of the program-
mable divider is frequency and phase locked to the comparison
frequency.
The reference frequency may be generated by an external
source capacitively coupled into pin 2 or provided by an on-
chip 4MHz crystal controlled oscillator.
Note that the comparison frequency is 7·8125kHz when a
4MHz reference is used.
Bit 2 of Byte 4 of the programming data (CP) controls the
current in the charge pump circuit, a logic 1 for
6170µA
and
a logic 0 for
650µA,
allowing compensation for the variable
tuning slope of the tuner and also to enable fast channel
changes over the full band. Bit 4 of Byte 4 (T0) disables the
charge pump if set to a logic 1. Bit 8 of Byte 4 (OS) switches
the charge pump drive amplifier’s output off when it is set to
a logic 1. Bit 3 of Byte 4 (T1) selects a test mode where the
phase comparator inputs are available on P6 and P7, a logic
1 connects F
COMP
to P6 and F
DIV
to P7.
Byte 5 programs the output ports P0-P7, a logic 0 for a high
impedance output, logic 1 for low impedance (on).
READ MODE
When the device is in the read mode the status data read
from the device on the SDA line takes the form shown in Table
2.
Bit 1 (POR) is the power on reset indicator and is set to a
logic 1 if the power supply to the device has dropped below a
nominal 3V and the programmed information lost (e.g., when
the device is initially turned on). The POR is set to 0 when the
read sequence is terminated by a stop command. The outputs
are all set to high impedance when the device is initially
powered up. Bit 2 (FL) indicates whether the device is phase
locked, a logic 1 is present if the device is locked and a logic
0 if the device is unlocked.
Bits 3, 4 and 5 (I2, I1, I0) show the status of the I/O Ports
P7, P5 and P4 respectively. A logic 0 indicates a low level and
a logic 1 a high level. If the ports are to be used as inputs they
should be programmed to a high impedance state (logic1).
These inputs will then respond to data complying with stand-
ard TTL voltage levels. Bits 6, 7 and 8 (A2,A1,A0) combine to
give the output of the 5-level ADC.
The 5-level ADC can be used to feed AFC information to
the microprocessor from the IF section of the television, as
illustrated in Fig. 4.
4
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