CD-700LACHDB-60.000 datasheet, PDF

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CD-700LACHDB-60.000: DescriptionPHASE LOCKED LOOP, CQCC16, HERMETIC SEALED, CERAMIC, SMD-16; CategoryAnalog mixed-signal IC The signal circuit; File Size147KB，14 Pages; ManufacturerVectron International, Inc.; Websitehttp://www.vectron.com/; Environmental Compliance

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CD-700LACHDB-60.000 Overview

PHASE LOCKED LOOP, CQCC16, HERMETIC SEALED, CERAMIC, SMD-16

CD-700LACHDB-60.000 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	SOIC
package instruction	QCCN,
Contacts	16
Reach Compliance Code	compliant
Analog Integrated Circuits - Other Types	PHASE LOCKED LOOP
JESD-30 code	R-CQCC-N16
JESD-609 code	e4
length	7.49 mm
Humidity sensitivity level	1
Number of functions	1
Number of terminals	16
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QCCN
Package shape	RECTANGULAR
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	2.13 mm
Maximum supply voltage (Vsup)	3.63 V
Minimum supply voltage (Vsup)	2.97 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
Temperature level	COMMERCIAL
Terminal surface	GOLD OVER NICKEL
Terminal form	NO LEAD
Terminal pitch	1.02 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	5.08 mm
Base Number Matches	1

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CD-700

Complete VCXO Based Phase Lock Loop

Features

•

5 x 7.5 x 2 mm, smallest VCXO PLL available

•

Output Frequencies to 65.536 MHz

•

5.0 or 3.3 Vdc operation

•

Tri-State Output

•

Loss of Signal Alarm

•

VCXO with CMOS outputs

•

0/70 or –40/85

°C

temperature range

•

Hermetically sealed ceramic SMD package

Applications

•

Frequency Translation

•

Clock Smoothing, Clock Switching

•

NRZ Clock recovery

LOS

(8)

PHO OPN

(3)

(2)

OPOUT

(1)

(16)

LOSIN

(4)

•

DSLAM, ADM, ATM, Aggregation, Optical

Switching/Routing, Base Station

•

Low jitter PLL’s

DATAIN

(5)

CLKIN

(6)

VCXO

Phase

Detector

and LOS

OP-Amp

OUT1

(13)

Description

Optional

2 Divider

OUT2

(11)

RCLK RDATA

(9)

(10)

OPP

(15)

GND

(7)

VDD

(14)

HIZ

(12)

The VI CD-700 is a user-configurable crystal

based PLL integrated circuit. It includes a digital

phase detector, op-amp, VCXO and additional

integrated functions for use in digital

synchronization applications. Loop filter software

is available as well SPICE models for circuit

simulation.

Figure 1. CD-700 Block Diagram

Vectron International 166 Glover Avenue, Norwalk CT 06856-5160

Tel:1-88-VECTRON-1

e-mail: vectron@vectron.com

CD-700, VCXO Based PLL

CD-700 Theory of Operation

Phase Detector

The phase detector has two buffered inputs (DATAIN and CLKIN) which are designed to switch at

1.4 volts. DATAIN is designed to accept an NRZ data stream but may also be used for clock signals which

have a 50% duty cycle. CLKIN is connected to OUT1 or OUT2, or a divided version of one of these

outputs. CLKIN and DATAIN and are protected by ESD diodes and should not exceed the power supply

voltage or ground by more than a few hundred millivolts.

The phase detector is basically a latched flip flop/exclusive-or gate/differential amplifier filter design to

produce a DC signal proportional to the phase between the CLKIN and DATAIN signals (see Figure 4 for

a block diagram and Figure 5 for an open loop transfer curve). This will simplify the PLL design as the

designer does not have to filter narrow pulse signals to a DC level. Under locked conditions the rising

edge of CLKIN will be centered in the middle of the DATAIN signal (see Figure 6).

The phase detector gain is 0.53V/rad x data density for 5volt operation and 0.35V/rad x data density for

3.3 volt operation. Data density is equal to 1.0 for clock signals and is system dependent on coding and

design for NRZ signals, but 0.25 could be used as a starting point for data density.

The phase detector output is a DC signal for DATAIN frequencies greater than 1 MHz but produces

significant ripple when inputs are less than 200 kHz. Additional filtering is required for lower input

frequencies applications such as 8kHz (see Figures 8 and 9 as examples).

Under closed loop conditions the active filter has a blocking capacitor which provides a very high DC gain,

so under normal locked conditions and input frequencies >1 MHz, PHO will be about V

/2 and will not

vary significantly with changes in input frequency (within lock range). The control voltage (pin 16) will vary

according to the input frequency offset, but PHO will remain relatively constant.

Data In

(pin 5)

Clock In

(pin 6)

30 kΩ

20 kΩ

PHO

(pin 3)

Gain = V

/ 2π

Gain = 2 / 3

Figure 4. Simplified Phase Detector Block Diagram

Vectron International

•

166 Glover Avenue, Norwalk, CT 06856

•

Tel: 1-88-VECTRON-1• http://www.vectron.com

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