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CAT24WC65JE-1.8TE13REVD

Description
EEPROM, 8KX8, Serial, CMOS, PDSO8, 0.150 INCH, MS-012, SOIC-8
Categorystorage    storage   
File Size637KB,12 Pages
ManufacturerCatalyst
Websitehttp://www.catalyst-semiconductor.com/
Download Datasheet Parametric View All

CAT24WC65JE-1.8TE13REVD Overview

EEPROM, 8KX8, Serial, CMOS, PDSO8, 0.150 INCH, MS-012, SOIC-8

CAT24WC65JE-1.8TE13REVD Parametric

Parameter NameAttribute value
Parts packaging codeSOIC
package instructionSOP,
Contacts8
Reach Compliance Codeunknown
ECCN codeEAR99
Maximum clock frequency (fCLK)0.1 MHz
JESD-30 codeR-PDSO-G8
length4.9 mm
memory density65536 bit
Memory IC TypeEEPROM
memory width8
Number of functions1
Number of terminals8
word count8192 words
character code8000
Operating modeSYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
organize8KX8
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialSERIAL
Certification statusNot Qualified
Maximum seat height1.75 mm
Serial bus typeI2C
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)1.8 V
Nominal supply voltage (Vsup)3 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
width3.9 mm
Maximum write cycle time (tWC)10 ms
Base Number Matches1
CAT24WC33/65
32K/64K-Bit I
2
C Serial CMOS EEPROM
FEATURES
I
400 KHz I
2
C Bus Compatible*
I
1.8 to 5.5 Volt Read and Write Operation
I
Cascadable for up to Eight Devices
I
32/64-Byte Page Write Buffer
I
Self-Timed Write Cycle with Auto-Clear
I
8-Pin DIP or 8-Pin SOIC
I
Schmitt Trigger Inputs for Noise Protection
I
Commercial, Industrial and Automotive Tem-
perature Ranges
I
Write Protection
I
1,000,000 Program/Erase Cycles
I
100 Year Data Retention
–Bottom 1/4 Array Protected When WP at V
IH
DESCRIPTION
The CAT24WC33/65 is a 32K/64K-bit Serial CMOS
E
2
PROM internally organized as 4096/8192 words of 8
bits each. Catalyst’s advanced CMOS technology sub-
stantially reduces device power requirements. The
CAT24WC33/65 features a 32-byte page write buffer.
The device operates via the I
2
C bus serial interface and
is available in 8-pin DIP or 8-pin SOIC packages.
PIN CONFIGURATION
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
DIP Package (P, L)
SOIC Package (J, W, K, X)
A0
A1
A2
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
PIN FUNCTIONS
Pin Name
A0, A1, A2
SDA
SCL
WP
V
CC
V
SS
i
D
VSS
c
s
Ground
u
n
i
t
n
o
VCC
WP
SCL
VCC
VSS
BLOCK DIAGRAM
DOUT
ACK
SENSE AMPS
SHIFT REGISTERS
EXTERNAL LOAD
d
e
START/STOP
LOGIC
CONTROL
LOGIC
a
P
s
t
r
COLUMN
DECODERS
256
SDA
WORD ADDRESS
BUFFERS
SDA
E
2
PROM
XDEC 128/256 128/256 X 256
WP
Function
DATA IN STORAGE
Device Address Inputs
Serial Data/Address
Serial Clock
Write Protect
+1.8V to +5.5V Power Supply
SCL
A0
A1
A2
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
HIGH VOLTAGE/
TIMING CONTROL
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I
2
C Bus Protocol.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
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