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SN74CBTR16861
20-BIT FET BUS SWITCH
SCDS078D – JULY 1998 – REVISED NOVEMBER 2001
D
D
D
D
D
Member of the Texas Instruments
Widebus Family
25-Ω Switch Connection Between Two
Ports
TTL-Compatible Input Levels
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
description
The SN74CBTR16861 provides 20 bits of
high-speed TTL-compatible bus switching. The
low on-state resistance of the switch allows
connections to be made with minimal propagation
delay.
The device is organized as one dual 10-bit switch
with separate output-enable (OE) inputs. When
OE is low, the switch is on, and port A is connected
to port B. When OE is high, the switch is open, and
the high-impedance state exists between the two
ports.
The device has equivalent 25-Ω series resistors to
reduce signal-reflection noise. This eliminates the
need for external terminating resistors.
NC
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
1A9
1A10
GND
NC
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2A9
2A10
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
V
CC
1OE
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
1B9
1B10
V
CC
2OE
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
2B9
2B10
NC – No internal connection
ORDERING INFORMATION
TA
PACKAGE†
SSOP – DL
–40°C to 85°C
40°C
TSSOP – DGG
TVSOP – DGV
Tube
Tape and reel
Tape and reel
Tape and reel
ORDERABLE
PART NUMBER
SN74CBTR16861DL
SN74CBTR16861DLR
SN74CBTR16861DGGR
SN74CBTR16861DGVR
TOP-SIDE
MARKING
CBTR16861
CBTR16861
CZ861
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
(each 10-bit bus switch)
INPUT
OE
L
H
FUNCTION
A port = B port
Disconnect
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2001, Texas Instruments Incorporated
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•
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1
SN74CBTR16861
20-BIT FET BUS SWITCH
SCDS078D – JULY 1998 – REVISED NOVEMBER 2001
logic diagram (positive logic)
2
1A1
46
1B1
11
1A10
37
1B10
1OE
47
14
2A1
34
2B1
23
2A10
25
2B10
2OE
35
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I
IK
(V
I/O
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance,
θ
JA
(see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN
VCC
VIH
VIL
TA
Supply voltage
High-level control input voltage
Low-level control input voltage
Operating free-air temperature
–40
4
2
0.8
85
MAX
5.5
UNIT
V
V
V
°C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
2
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SN74CBTR16861
20-BIT FET BUS SWITCH
SCDS078D – JULY 1998 – REVISED NOVEMBER 2001
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
II
ICC
∆I
CC‡
Ci
VCC = 4.5 V,
VCC = 0,
VCC = 5.5 V,
VCC = 5.5 V,
Control inputs
Control inputs
VCC = 5.5 V,
VI = 3 V or 0
VO = 3 V or 0,
VCC = 4 V,
TYP at VCC = 4 V
VCC = 4.5 V
TEST CONDITIONS
II = –18 mA
VI = 5.5 V
VI = 5.5 V or GND
IO = 0,
One input at 3.4 V,
OE = VCC
VI = 2.4 V,
VI = 0
II = 15 mA
II = 64 mA
II = 30 mA
20
20
20
VI = VCC or GND
Other inputs at VCC or GND
3.5
5
37
33
33
50
47
47
Ω
MIN
TYP†
MAX
–1.2
10
±1
3
2.5
UNIT
V
µA
µA
mA
pF
pF
Cio(OFF)
ron§
VI = 2.4 V,
II = 15 mA
20
35
48
† All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C.
‡ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
§ Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lowest voltage of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
tpd¶
ten
tdis
FROM
(INPUT)
A or B
OE
OE
TO
(OUTPUT)
B or A
A or B
A or B
3.1
2.7
VCC = 4 V
MIN
MAX
1.25
9
6.3
2.7
2.3
VCC = 5 V
±
0.5 V
MIN
MAX
1.25
8.6
6.9
ns
ns
ns
UNIT
¶ The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
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3
SN74CBTR16861
20-BIT FET BUS SWITCH
SCDS078D – JULY 1998 – REVISED NOVEMBER 2001
PARAMETER MEASUREMENT INFORMATION
7V
From Output
Under Test
CL = 50 pF
(see Note A)
500
Ω
S1
Open
GND
500
Ω
Output
Control
(low-level
enabling)
tPZL
3V
Input
1.5 V
1.5 V
0V
tPLH
Output
1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPHL
VOH
1.5 V
VOL
Output
Waveform 1
S1 at 7 V
(see Note B)
tPZH
Output
Waveform 2
S1 at Open
(see Note B)
1.5 V
1.5 V
TEST
tpd
tPLZ/tPZL
tPHZ/tPZH
S1
Open
7V
Open
3V
1.5 V
1.5 V
0V
tPLZ
3.5 V
VOL + 0.3 V
tPHZ
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOL
LOAD CIRCUIT
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤
10 MHz, ZO = 50
Ω,
tr
≤
2.5 ns, tf
≤
2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
4
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