ACT7005/7006
Single Package Solution
Dual Transceiver, Protocol, Subsystem
Features
• Incorporates Transceivers, Protocol, and System Interface Components into a
Single Hybrid Package
• Functions as a Remote Terminal or Bus Controller
• Interfaces to µP as a Simple Peripheral Unit
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• +5V Operation
• Provides 2k by 16 of Double Buffered RAM Storage for Transmit and Receive
Subaddresses
• Pin Programmable for 8-bit or 16-bit Microprocessors
• Full Military (-55°C to +125°C) Temperature Range
General Description
The ACT7005/6 Series provides a complete one package interface between the MIL-STD-1553 bus and all
microprocessor systems. The hybrid provides all data buffers and control registers to function as a Bus
Controller or Remote Terminal. Control of the hybrid by the subsystem is through simple I/O port commands.
Internal hybrid logic removes all critical timing imposed on a typical subsystem, thereby simplifying the
implementation of this interface.
INTERRUPTS/
CONTROL
SIGNALS
µP
INTERFACE
BUS "0"
DUAL
TX/RX
1553
PROTOCOL
S
U
B
S
Y
S
T
E
M
8/16
BIT
I/O
RAM
BUS "1"
ACT7005 / ACT7006
Block Diagram
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echnology
– Data Bus Modules For The Future © SCD7005 REV B 8/2/01
Aeroflex Circuit Technology
8 BIT INTERNAL HIGHWAY
RT Command Word Register
MUX
ENCODER
INTERFACE
UNIT
RECEIVE
FIFO
BUFFER
TRANSMIT
FIFO
BUFFER
Receive Command Register
Command Word #1 Register
32 x 16
32 x 16
VW/CMD Word #2/AMD Register
MUX
DECODER "0"
1k x 16
Sync/Stat WD #2/RMD Register
RECEIVE
RAM
Operation Register
Driver
Select
and
Enable
DECODER "1"
MUX
1k x 16
INPUT
FIFO
BUFFER
OUTPUT
FIFO
BUFFER
SELF TEST
CIRCUITRY
STATUS
WORD
CONTROL
TRANSMIT
RAM
Status Word #1 Register
INTERNAL
HIGHWAY
CONTROL
ARBITRATION
AND
CONTROL LOGIC
32 x 16
32 x 16
BI-DIRECTIONAL
I/O DATA BUFFER
8 or 16 BIT SYSTEMS BUS
HANDSHAKE and CONTROL SIGNALS
Control Signals and Interrupts
ADDRESS
DISCRETE INPUT/OUTPUT SIGNALS
BUS "0"
Transceiver
"0"
2
BUS "1"
Transceiver
"1"
Terminal
Address
Inputs
SCD7005 REV B 8/2/01
Plainview NY (516) 694-6700
Figure 1 – FUNCTIONAL BLOCK DIAGRAM
Parameter
Power Supply Voltage (V
CC
)
Power Supply Voltage (V
CCL
& V
DD
)
Receiver Differential Input
(DATA CH A/B / DATA CH A/B)
Receiver Input Voltage
(DATA CH A/B or DATA CH A/B – Common Mode)
Operating Case Temperature Range (T
C
)
Transmission Duty Cycle at T
C
= +125°C
Min
-0.3
-0.3
-10
-5
-55
-
Max
7.0
7.0
+10
+5
+125
100
Units
V
V
V
V
°C
%
Table 1 – Absolute Maximum Ratings
Parameter/Condition
Power Supply Voltage
Total supply current "standby" mode or transmitting at
less than 1% duty cycle (e.g. 20µs of transmission every
2ms or longer interval). 2/
Total supply current transmitting at 1MHz into a 35Ω load
at Point A in Figure 1. 2/ 1/
Note:
1/
2/
Symbol
V
CC
I
CC
@1
%
Min
4.75
Typ
5
18
Max
5.5
30
Unit
mA
mA
I
CC
@
25%
I
CC
@
50%
I
CC
@
100%
150
300
600
175
350
700
mA
mA
mA
Decreases linearly to applicable "standyby" values at zero duty cycle.
Represents one channel only.
Table 2 – Analog Transceiver Power Supply Characteristics
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3
SCD7005 REV B 8/2/01
Plainview NY (516) 694-6700
Parameter/Condition
Differential impedance DC to 1MHz,
See Figure 4
Differential voltage range
Input common mode voltage range
Common mode rejection ratio (from point A, Figure 4)
Threshold characteristics (sine wave at 1MHz)
NOTE: Threshold voltages refer Figure 4
Point A
Point C
Point A
Point C
Symbol
Z
IO
Min
2K
1K
Max
Unit
Ω
Ω
V
DIR
V
ICR
CMRR
V
TH
1
V
TH
2
-10
-5
40
0.8
0.56
+10
+5
V
PEAK
V
PEAK
dB
1.1
0.86
Vp-p
Vp-p
Table 3 – Analog Transceiver Electrical Characteristics (Receiver Section)
(Over Full Temperature Range)
Parameter / Condition
Differential output level at point B,
See Figure 4
140Ω Point B
70Ω Point C
Differential Output Noise at Point A, See Figure 4
Output Offset at point A in Figure 4,
2.5µs after mid-bit crossing of parity bit
of last word of a 660µs message
Point A (35Ω)
Point C (70Ω)
Symbol
V
O
Min
24
18
Typ
Max
35
25
10
Unit
Vp-p
Vp-p
mVp-p
mV
mV
ns
V
NOI
Vos
1
Vos
2
-90
-250
100
160
+90
+250
300
Rise and Fall times (10% to 90% of p-p output)
t
R
&
t
F
Table 4 – Analog Transceiver Electrical Characteristics (Transmitter Section)
(Over Full Temperature Range)
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4
SCD7005 REV B 8/2/01
Plainview NY (516) 694-6700
Symbol
V
DD
V
IH
V
IL
I
L
I
IH
I
L
I
IH
I
L
I
IH
V
OH
V
OL
V
DD
V
DD
Parameter
Logic Supply
Input "1"
Input "0"
Input I
Input I
Input I
Input I
Input I
Input I
Output "1"
Output "0"
Static I
Dynamic I
Min
4.5
2.4
Typ
5.0
Max
5.5
Units
VDC
V
Conditions
0.6
-450
-250
-50
-50
-25
-25
2.4
0.4
50
170
-600
-400
-200
-200
-125
-125
-900
-750
-800
-800
-400
-400
V
µA
µA
µA
µA
µA
µA
VDC
VDC
mA
mA
Note 1A
Note 1B
Note 1C
Note 1D
Note 2A
Note 2B
Note 3A
Note 3B
Note 4A
Note 4B
Notes:
1. V
DD
= 5.5V
A. For RTAD0/1/2/3/4 and RTADPAR with VIL = 0.4V
B. For RTAD0/1/2/3/4 and RTADPAR with VIH = 2.4V
C. FOR BCSTEN WITH VIL = 0.4V, Test 1, 6MHz
D. FOR BCSTEN WITH VIH = 2.4V, Test 1, 6MHz
2.
All remaining inputs and I/O
VDD = 5.5V
A. VIL = 0.4V
B. VIH = 2.4V
A. VDD = 4.5V and IOH = 3mA
B. VDD = 5.5V and IOL = 3mA
VDD = 5.5V
A. Clock Input = 6MHz (45-55% Duty Cycle / TTL Levels), All remaining inputs = VDD,
All Outputs = Open Circuit
B. During a 32 word FIFO to RAM or RAM to FIFO block
move
.
3.
4.
Table 5 – Logic Electrical Characteristics
(Over Full Temperature Range)
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SCD7005 REV B 8/2/01
Plainview NY (516) 694-6700
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