EDI88512CA55CC datasheet, PDF - EEWORLD Datasheet

EDI88512CA55CC: DescriptionStandard SRAM, 512KX8, 55ns, CMOS, CDIP32, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-32; Categorystorage storage; ManufacturerMicrosemi; Websitehttps://www.microsemi.com

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EDI88512CA55CC Overview

Standard SRAM, 512KX8, 55ns, CMOS, CDIP32, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-32

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	DIP
package instruction	0.600 INCH, SIDE BRAZED, CERAMIC, DIP-32
Contacts	32
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	55 ns
Other features	TTL COMPATIBLE INPUTS/OUTPUTS
JESD-30 code	R-CDIP-T32
length	40.64 mm
memory density	4194304 bit
Memory IC Type	STANDARD SRAM
memory width	8
Number of functions	1
Number of terminals	32
word count	524288 words
character code	512000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512KX8
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	3.937 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15.24 mm
Base Number Matches	1

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