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2.5 V/3.3 V, Four LVPECL Outputs,
SiGe Clock Fanout Buffer
ADCLK944
FEATURES
Operating frequency: 7.0 GHz
Broadband random jitter: 50 fs rms
On-chip input terminations
Power supply (V
CC
− V
EE
): 2.5 V to 3.3 V
FUNCTIONAL BLOCK DIAGRAM
ADCLK944
LVPECL
Q0
V
REF
Q0
REFERENCE
Q1
V
T
CLK
Q2
CLK
Q3
Q3
08770-001
APPLICATIONS
Low jitter clock distribution
Clock and data signal restoration
Level translation
Wireless communications
Wired communications
Medical and industrial imaging
ATE and high performance instrumentation
Q1
Q2
Figure 1.
GENERAL DESCRIPTION
The ADCLK944 is an ultrafast clock fanout buffer fabricated on
the Analog Devices, Inc., proprietary XFCB3 silicon germanium
(SiGe) bipolar process. This device is designed for high speed
applications requiring low jitter.
The device has a differential input equipped with center-tapped,
differential, 100 Ω on-chip termination resistors. The input can
accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended),
and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A V
REF
pin is available for biasing ac-coupled inputs.
The ADCLK944 features four full-swing emitter-coupled logic
(ECL) output drivers. For LVPECL (positive ECL) operation,
bias V
CC
to the positive supply and V
EE
to ground. For ECL
operation, bias V
CC
to ground and V
EE
to the negative supply.
The ECL output stages are designed to directly drive 800 mV
each side into 50 Ω terminated to V
CC
− 2 V for a total differen-
tial output swing of 1.6 V.
The ADCLK944 is available in a 16-lead LFCSP and is specified
for operation over the standard industrial temperature range of
−40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
ADCLK944
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Clock Inputs and Outputs ........................................................... 3
Timing Characteristics ................................................................ 3
Power .............................................................................................. 4
Absolute Maximum Ratings............................................................ 5
Determining Junction Temperature .......................................... 5
ESD Caution...................................................................................5
Thermal Performance ...................................................................5
Pin Configuration and Function Descriptions..............................6
Typical Performance Characteristics ..............................................7
Theory of Operation .........................................................................9
Clock Inputs ...................................................................................9
Clock Outputs ................................................................................9
PCB Layout Considerations ...................................................... 10
Input Termination Options ....................................................... 11
Outline Dimensions ....................................................................... 12
Ordering Guide .......................................................................... 12
REVISION HISTORY
3/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 12
ADCLK944
SPECIFICATIONS
Typical values are given for V
CC
− V
EE
= 3.3 V and T
A
= 25°C, unless otherwise noted. Minimum and maximum values are given for the
full V
CC
− V
EE
= 3.3 V + 10% to 2.5 V − 5% and T
A
= −40°C to +85°C variation, unless otherwise noted.
CLOCK INPUTS AND OUTPUTS
Table 1.
Parameter
DC INPUT CHARACTERISTICS
Input Common-Mode Voltage
Input Differential Voltage
Input Capacitance
Input Resistance
Single-Ended Mode
Differential Mode
Common Mode
Input Bias Current
DC OUTPUT CHARACTERISTICS
Output Voltage High Level
Output Voltage Low Level
Output Voltage, Single-Ended
Voltage Reference
Output Voltage
Output Resistance
Symbol
V
ICM
V
ID
C
IN
R
IN
Min
V
EE
+ 1.35
0.4
0.4
50
100
50
20
V
OH
V
OL
V
O
V
REF
V
CC
− 1.26
V
CC
− 1.99
600
(V
CC
+ 1)/2
250
V
CC
− 0.76
V
CC
− 1.54
960
Typ
Max
V
CC
− 0.1
3.4
Unit
V
V p-p
pF
Ω
Ω
kΩ
μA
V
V
mV
V
Ω
Test Conditions/Comments
±1.7 V between input pins
V
T
open
Load = 50 Ω to (V
CC
− 2.0 V)
Load = 50 Ω to (V
CC
− 2.0 V)
V
OH
− V
OL
, output static
−500 μA to +500 μA
TIMING CHARACTERISTICS
Table 2.
Parameter
AC PERFORMANCE
Maximum Output Frequency
Output Rise/Fall Time
Propagation Delay
Temperature Coefficient
Output-to-Output Skew
1
Part-to-Part Skew
Additive Time Jitter
Integrated Random Jitter
Broadband Random Jitter
2
CLOCK OUTPUT PHASE NOISE
Absolute Phase Noise
f
IN
= 1 GHz
Symbol
Min
6.2
t
R
t
PD
35
70
Typ
7.0
50
100
75
75
130
15
35
26
50
Max
Unit
GHz
ps
ps
fs/°C
ps
ps
fs rms
fs rms
Test Conditions/Comments
Differential output voltage swing > 0.8 V
(see Figure 4)
20% to 80%, measured differentially
V
ID
= 1.6 V p-p
V
ID
= 1.6 V p-p
BW = 12 kHz to 20 MHz, CLK = 1 GHz
V
ID
= 1.6 V p-p, 8 V/ns, V
ICM
= 2 V
Input slew rate > 1 V/ns (see Figure 11)
100 Hz offset
1 kHz offset
10 kHz offset
100 kHz offset
>1 MHz offset
−118
−135
−144
−150
−150
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
1
2
The output-to-output skew is the difference between any two similar delay paths while operating at the same voltage and temperature.
Measured at the rising edge of the clock signal; calculated using the SNR of the ADC method.
Rev. 0 | Page 3 of 12
ADCLK944
POWER
Table 3.
Parameter
POWER SUPPLY
Supply Voltage Requirement
Power Supply Current
Negative Supply Current
Positive Supply Current
Power Supply Rejection
1
Output Swing Supply Rejection
2
1
2
Symbol
V
CC
− V
EE
I
VEE
I
VEE
I
VCC
I
VCC
PSR
VCC
PSR
VCC
Min
2.375
Typ
Max
3.63
Unit
V
mA
mA
mA
mA
ps/V
dB
Test Conditions/Comments
3.3 V + 10% to 2.5 V − 5%
Static
V
CC
− V
EE
= 2.5 V ± 5%
V
CC
− V
EE
= 3.3 V ± 10%
V
CC
− V
EE
= 2.5 V ± 5%
V
CC
− V
EE
= 3.3 V ± 10%
35
37
139
138
−3
28
49
165
Change in t
PD
per change in V
CC
.
Change in output swing per change in V
CC
.
Rev. 0 | Page 4 of 12
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