High-stability Crystal Oscillator IC with Frequency Adjustment Function
OVERVIEW
The 5041 series are high-stability clock oscillator ICs with built-in frequency adjustment functions. The
frequency adjustment functions can be optimized, by the addition of a minimal adjustment process, to improve
the frequency stability. The function is implemented using frequency adjustment data written to a built-in
EEPROM over a 1-wire serial interface. The ICs are ideal for compact crystal oscillators for use in applications
such as WiMAX (Worldwide Interoperability for Microwave Access) and PLC (Power Line Communication)
that require high frequency stability in the order of
±30
to
±10ppm.
They use a pad layout suitable for flip chip
bonding mounting.
FEATURES
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Realizing frequency stability improvement with
minimal additional process
Temperature compensation range/ operating tem-
perature range:
−40°C
to +85°C
Frequency adjustment functions built-in
• Frequency-temperature characteristics compen-
sation function
AT-cut crystal, 3rd order harmonic frequency-
temperature characteristics compensation, with
independent low-temperature and high-temper-
ature range compensation settings
- Center frequency adjustment function
- Temperature rotation compensation function
- Low-temperature characteristics compensation
- High-temperature characteristics compensation
Rewritable EEPROM built-in
6 pads: same as general clock oscillator ICs
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Operating supply voltage range
• 5041A
××
: 2.25V to 3.63V
• 5041B
×
A: 1.60V to 2.25V
Recommended oscillation frequency range:
20MHz to 55MHz (for fundamental oscillation)
Frequency divider built-in:
• Selectable by version: f
O
, f
O
/2, f
O
/4, f
O
/8, f
O
/16,
f
O
/32
• Frequency divider output for 0.625MHz (min)
low frequency output
Standby function
High-impedance in standby mode, oscillator stops
CMOS output
15pF output load
Pad layout for flip chip bonding
Wafer form (WF5041×××)
FREQUENCY CHARACTERISTICS COMPENSATION BEFORE and AFTER ADJUSTMENT
50
40
30
20
∆f/f
[ppm]
10
0
−10
−20
−30
−40
−50
−40 −20
0
20
40
Ta [°C]
60
80
100
After compensation
±
10ppm
Before compensation
APPLICATIONS
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3.2mm
×
2.5mm, 2.5mm
×
2.0mm, 2.0mm
×
1.6mm size miniature crystal oscillator modules
WiMAX, WiBro, PLC and applications requiring high-stability clock oscillators
ORDERING INFORMATION
Device
WF5041×××−4
Package
Wafer form
SEIKO NPC CORPORATION—1
5041 series
SERIES CONFIGURATION
Operating
Recommended
supply
oscillation
frequency range
*1
voltage range
[V]
[MHz]
2.25 to 3.63
20 to 55
1.60 to 2.25
2
(1)
5041A1B
(5041B1A)
5041A2B
(5041B2A)
5041A3B
(5041B3A)
5041A4B
(5041B4A)
5041A5B
(5041B5A)
5041A6B
(5041B6A)
Temperature
adjustment
function gain
setting ratio
*2
1
for flip chip
bonding
Output frequency and version name
*3
f
O
5041A1A
f
O
/2
5041A2A
f
O
/4
5041A3A
f
O
/8
5041A4A
f
O
/16
5041A5A
f
O
/32
5041A6A
Pad layout
*1. The recommended oscillation frequency is a yardstick value derived from the crystal used for NPC characteristics authentication. However, the oscilla-
tion frequency range is not guaranteed. Specifically, the characteristics can vary greatly due to crystal characteristics and mounting conditions, so the
oscillation characteristics of components must be carefully evaluated.
*2. Values in parentheses ( ) are provisional only.
*3. Versions in parentheses ( ) are under development.
TEMPERATURE ADJUSTMENT FUNCTION GAIN SETTING RATIO
Temperature adjustment function gain setting ratio of 5041A×A and 5041A×B differs. In the case of tempera-
ture adjustment function that rotates temperature characteristics on T
0
origin, adjustment sensitivity of
5041A
×
B is designed twice as higher than that of 5041A
×
A based on non-compensation temperature deviation
in same register value setting.
5041A×A
5041A×B
Frequency [MHz]
<Gain setting ratio>
5041A×A : 5041A×B
1 : 2
T
0
Temperature deviation
at non-compensation
Ta [°C]
VERSION NAME
Device
Package
Version name
WF5041
WF5041
×××−
4
Wafer form
Form WF: Wafer form
−4
Temperature adjustment function gain setting ratio
Frequency divider function (output frequency)
Operating supply voltage
SEIKO NPC CORPORATION—2
5041 series
PAD LAYOUT
(Unit:
µm)
(420,345)
VSS
Y INHN
5
6
1
(−420,−345)
XT
X
(0,0)
2
XTN
4
3
Q
VDD
Chip size: 0.84mm
×
0.69mm
Chip thickness: 130µm
±
15µm
Pad size: 80µm
×
80µm
Chip base: V
SS
level
PAD DIMENSIONS
Pad No.
1
2
3
4
5
6
Pin
XT
XTN
VDD
Q
VSS
INHN
I/O
I
O
–
O
–
I
PIN DESCRIPTION
Pad dimensions [µm]
Name
Amplifier input
Amplifier output
(+) supply voltage
Output
(–) ground
Output state control input
Description
X
Crystal connection pins.
Crystal is connected between XT and XTN.
–
Output frequency determined by internal circuit
to one of f
O
, f
O
/2, f
O
/4, f
O
/8, f
O
/16, f
O
/32.
High impedance in standby mode
–
High impedance when LOW (oscillator stops).
Power-saving pull-up resistor built-in.
–225.2
225.2
328.5
328.5
–328.5
–328.5
Y
–253.5
–253.5
–5.0
223.8
223.8
–5.0
BLOCK DIAGRAM
XT
R
V
R
F
R
V
Regulator
*2
1
N
*1
Oscillation
Detection
XTN
VDD
Q
INHN
Temperature
Compensation
VSS
Control Register
FO, TO, RTG, TLO, TLG,
THO, THG
*1. N = 1, 2, 4, 8, 16, 32 (mask option)
*2. 5041A
××
version only
SEIKO NPC CORPORATION—3
5041 series
ABSOLUTE MAXIMUM RATINGS
V
SS
=
0V unless otherwise noted.
Parameter
Supply voltage range
Program read/write supply voltage
range
Input voltage range
*1
Output voltage range
*1
Output current
Storage temperature range
EEPROM maximum writes
Symbol
V
DD
V
PP
V
IN
V
OUT
I
OUT
T
STG
N
EW
Conditions
Between VDD and VSS
Between INHN and VSS
Input pins
Output pins
Q pin
Wafer form
Rating
−0.3
to
+4.0
−0.3
to
+16.5
−0.3
to V
DD
+
0.3
−0.3
to V
DD
+
0.3
±
20
−65
to
+150
100
Unit
V
V
V
V
mA
°C
times
*1. V
DD
is a V
DD
value of recommended operating conditions.
Note. Absolute maximum ratings are the values that must never exceed even for a moment. This product may suffer breakdown if any one of these
parameter ratings is exceeded. Operation and characteristics are guaranteed only when the product is operated at recommended supply voltage
range.
RECOMMENDED OPERATING CONDITIONS
V
SS
=
0V unless otherwise noted.
Rating
*1
Parameter
Symbol
Conditions
Min
5041A××
Supply voltage
Input voltage
Operating temperature
Oscillation frequency
*2
V
DD
V
IN
T
OPR
5041A××
fo
5041B×A
Output frequency
*2
Output load capacitance
5041A××
f
OUT
C
LOUT
Q pin
5041B×A
Q pin
(0.625)
–
–
–
(55)
15
MHz
pF
(20)
0.625
–
–
(55)
55
MHz
MHz
Between VDD and VSS
5041B×A
Input pins (XT, INHN)
1.60
V
SS
−40
20
–
–
–
–
2.25
V
DD
+85
55
V
V
°C
MHz
2.25
Typ
–
Max
3.63
V
Unit
*1. Values in parentheses ( ) are provisional only.
*2. The recommended oscillation frequency is a yardstick value derived from the crystal used for NPC characteristics authentication. However, the oscilla-
tion frequency range is not guaranteed. Specifically, the characteristics can vary greatly due to crystal characteristics and mounting conditions, so the
oscillation characteristics of components must be carefully evaluated.
SEIKO NPC CORPORATION—4
5041 series
ELECTRICAL CHARACTERISTICS
DC Characteristics (5041A1× to A6×)
V
DD
=
2.25V to 3.63V, V
SS
=
0V, Ta
= −40°C
to
+85°C,
C
LOUT
= 15pF unless otherwise noted.
Rating
Parameter
Symbol
Conditions
MIN
5041A1× (f
OUT
= fo),
Measurement circuit 1, no load,
INHN
=
HIGH, fo
=
48MHz
5041A2× (f
OUT
= fo/2),
Measurement circuit 1, no load,
INHN
=
HIGH, fo
=
48MHz
5041A3× (f
OUT
= fo/4),
Measurement circuit 1, no load,
INHN
=
HIGH, fo
=
48MHz
5041A4× (f
OUT
= fo/8),
Measurement circuit 1, no load,
INHN
=
HIGH, fo
=
48MHz
5041A5× (f
OUT
= fo/16),
Measurement circuit 1, no load,
INHN
=
HIGH, fo
=
48MHz
5041A6× (f
OUT
= fo/32),
Measurement circuit 1, no load,
INHN
=
HIGH, fo
=
48MHz
Standby-mode current
consumption
HIGH-level output voltage
LOW-level output voltage
Output leakage current
HIGH-level input current
LOW-level input current
INHN pull-up resistance
I
ST
V
OH
V
OL
I
Z
V
IH
V
IL
R
PU1
R
PU2
Measurement circuit 6
INHN
=
V
SS
INHN
=
0.7V
DD
V
DD
=
2.5V
V
DD
=
3.3V
V
DD
=
2.5V
V
DD
=
3.3V
V
DD
=
2.5V
V
DD
=
3.3V
V
DD
=
2.5V
V
DD
=
3.3V
V
DD
=
2.5V
V
DD
=
3.3V
V
DD
=
2.5V
V
DD
=
3.3V
–
–
–
–
–
–
–
–
–
–
–
–
–
V
DD
−0.4
–
–
−10
0.7V
DD
–
0.4
50
TYP
1.4
1.7
1.1
1.4
1.0
1.2
0.9
1.0
0.8
1.0
0.8
1.0
–
–
–
–
–
–
–
1.5
100
MAX
2.8
3.4
2.2
2.7
1.9
2.4
1.7
2.1
1.7
2.0
1.6
2.0
10
–
0.4
10
–
–
0.3V
DD
10
200
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
V
V
µA
µA
V
V
MΩ
kΩ
Unit
Operating-mode current
consumption
*1
I
DD
Measurement circuit 1, INHN
=
LOW
Q pin, Measurement circuit 3, I
OH
=
−4mA
Q pin, Measurement circuit 3, I
OL
=
4mA
Measurement circuit 4,
INHN
=
LOW
INHN pin, Measurement circuit 5
Q
=
V
DD
Q
=
V
SS
*1. The consumption current I
DD
(C
LOUT
) with a load capacitance (C
LOUT
) connected to the Q pin is given by the following equation, where I
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