INSSTU32866
INSSTUA32866
INSSTUB32866
DDR2 Configurable
Registered Buffer
with Parity Checking
Data Sheet
Applications
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High Performance Workstations
Mid and High Performance Servers
High Reliability Systems
Features
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INSSTU32866 meets or exceeds all JESD82-10 performance specifications for DDR2-400 and
DDR2-533 rates
The A and B versions meet or exceed all JESDxx-x performance specifications for DDR2-400,
DDR2-533, DDR2-667, and DDR2-800 rates
Supports RDIMM modules A, B, C, E, F, G, H, J, N
Complies with DDR2 SDRAM Over/Undershoot specification as defined in JESD79-2
Available in 96-Ball LFBGA (standard 0.8 mm ball pitch) and TFBGA (fine 0.65 mm ball pitch),
“Green” Package types
Pull-down resistors on all data and parity inputs
Latch-up exceeds JESD78 class 2
ESD protection exceeds JESD22
Passed Intel Validation
Available in Industrial Temperature Range (-40 °C to +85 °C)
Description
This configurable 25-bit 1:1 or 14-bit 1:2
register is designed for nominal 1.8V power
supply operation.
All inputs are SSTL_18
compatible except for the 1.8V LVCMOS reset
(
RESET ) and configuration control inputs (C0
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and C1). The INSSTU32866 operates with a
differential clock input (CK and CK ). Input data
is registered at the crossing point of rising CK and
falling CK .
Inphi Proprietary
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In typical Registered DIMM applications,
the outputs on these devices can each drive up to
10 SDRAM input loads.
The C1 input bit sets the pinout
configuration to 25-bit 1:1 (when low) or to 14-bit
1:2 (when high). The C0 input bit sets the
operating mode of the 1:2 configuration to
register-A configuration (when low) or to
register-B configuration (when high). All outputs
are edge-controlled circuits that are designed to
meet SSTL_18 specifications.
INSSTU32866
supports
low-power
standby mode. When RESET is low, the clock,
data, and reference voltage (V
REF
) input receivers
are disabled and floating clock, data, and reference
inputs are allowed. Additionally, all registers are
reset, and all outputs are forced low.
The RESET , C1, and C0 inputs must be
held at a valid logic level.
Asynchronous
transitions of RESET are supported. RESET
must be held low during power-up to ensure well-
defined outputs from the register after a stable
clock has been applied. The INSSTU32866
continually evaluates parity of the data inputs and
a parity input bit generated by the memory
controller (PAR_IN). Valid parity is defined as
even, i.e. an even number of ones among the data
inputs and PAR_IN. The DIMM-dependent
DCKE,
DCS
, DODT, and
CSR
are omitted
from parity evaluation.
When the INSSTU32866 is used as a
single device (C0=0, C1=0), the parity is evaluated
on the PAR_IN input, which arrives one cycle
after the corresponding input data. The partial-
parity-out (PPO) and parity error (
QERR ) output
signals are generated three positive transitions
after the corresponding data inputs and two
positive transitions after the corresponding
PAR_IN bit.
When the INSSTU32866 is used in pairs,
the first device has C0=0 and C1=1. The second
device has C0=1 and C1=1. The parity is
evaluated on the PAR_IN input of the first
device, which arrives one positive transition after
the corresponding input data. The PPO signal of
the first device, which is generated two positive
transitions after the corresponding data input and
one positive transition after the corresponding
PAR_IN, then drives PAR_IN of the second
device. The second device completes evaluation
of the full data word by evaluating its PAR_IN bit
(PPO of the first device) together with the
remaining data bits. The QERR signal is
generated three positive transitions after the data
input and two positive transitions after the parity
bit from the memory controller is applied to
PAR_IN of the first device. If a parity error
occurs, the QERR goes low and remains low for
two clock positive transitions, or until RESET is
driven low.
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Part Number Selection Table
This register is certified for use on the Raw Cards listed below as defined in JESD21-C, DDR2 Registered
DIMM Design Specification. It is guaranteed to produce over/undershoots less than indicated in the table
below to comply with DDR2 SDRAM Over/Undershoot requirements under worst-case DRAM loading
conditions (Min or Max), DIMM operating conditions and operated within the recommend operating
conditions listed in Table 5.
Inphi Product
Part Number
INSSTU32866
RDIMM
Speed Bin
Module
A, B, C, E, F, G, H, J, N
400, 533
Max
Overshoot
0.5V
Max
Undershoot
0.5V
INSSTUA32866
A, B, C, E, F, G, H, J, N
400, 533, 667
0.5V
0.5V
0.5V
0.5V
INSSTUB32866
A, B, C, E, F, G, H, J, N 400, 533, 667, 800
Terminal Functions
Terminal
Name
Description
Electrical
Characteristics
GND
V
DD
V
REF
CK
CK
C0, C1
RESET
CSR ,
DCS
D1-D25
1
DODT,
DCKE
PAR_IN
Q1-Q25
2
PPO
QCS
Ground
Power supply
Input reference voltage
Clock input
Complementary clock input
Configuration control inputs
Asynchronous reset input: resets registers and disables V
REF
, data and
clock input receivers
Chip select inputs - disables D1-D25 output switching when both
inputs are high
Data inputs - clocked in on the crossing of rising edge of CK and
falling edge of CK
The outputs of these register bits will not be suspended by the
CSR and DCS control
Parity input – arrives one clock cycle after corresponding data input
Data outputs that are suspended by the CSR and DCS control
Partial parity out – indicates odd parity of data bits D1-D25
1
and
corresponding PAR_IN
Data output that is not suspended by the CSR and DCS control
Ground
1.8 V nominal
0.9 V nominal
Differential input
Differential input
LVCMOS inputs
LVCMOS input
SSTL_18 inputs
SSTL_18 inputs
SSTL_18 inputs
SSTL_18 input
1.8 V CMOS
outputs
1.8 V CMOS
output
1.8 V CMOS
output
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Inphi Proprietary
Terminal Functions
Terminal
Name
Description
Electrical
Characteristics
QODT,
QCKE
QERR
NC
DNU
Data outputs that are not suspended by the CSR and DCS control
Parity error output – generated two cycles after corresponding data
output
No connect. Ball present but no internal connection to the die.
Do not use. Ball internally connected to the die and should be left
open-circuit.
1.8 V CMOS
outputs
Open-drain output
May connect to
PCB
Do not connect to
PCB
Notes:
1
Data inputs are D2, D3, D5, D6, D8-25 when C0=C1=0
Data inputs are D2, D3, D5, D6, D8-14 when C0=0, C1=1
Data inputs are D1-6, D8-10, D12, D13 when C0=C1=1
2
Data outputs are Q2, Q3, Q5, Q6, Q8-25 when C0=C1=0
Data outputs are Q2, Q3, Q5, Q6, Q8-14 when C0=0, C1=1
Data outputs are Q1-6, Q8-10, Q12, Q13 when C0=C1=1
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Block Diagrams
Logic diagram for 1:1 Register configuration (C0=0, C1=0)
G2
RESET
H1
CLK
J1
CLK
V
A3, T3
A1
REF
D1 (DCKE)
D
CLK
R
Q
Q1 (QCKE)
A5
D1
D4 (DODT)
D
CLK
R
Q
Q4 (QODT)
D5
H2
D7 (DCS)
D
CLK
R
Q
Q7 (QCS)
H5
J2
CSR
1
B1
D2
D
0
CLK
R
Q
B5
Q2
One of 22 Channels
To 21 other channels (D3, D5, D6, D8 through D25)
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