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XC25BS8047MR

Description
Ultra Small PLL Clock Generator ICs with Built-In Divider/Multiplier Circuits
File Size594KB,14 Pages
ManufacturerTOREX
Websitehttp://www.torex.co.jp/chinese/
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XC25BS8047MR Overview

Ultra Small PLL Clock Generator ICs with Built-In Divider/Multiplier Circuits

XC25BS8
Series
■GENERAL
DESCRIPTION
ETR1506-007a
Ultra Small PLL Clock Generator ICs with Built-In Divider/Multiplier Circuits
The XC25BS8 series is an ultra small PLL clock generator IC which can generate a high multiplier output up to 4095 from an input frequency as
low as 8kHz.
The series includes a divider circuit, phase/frequency comparator, charge pump, and VCO so it is possible to configure a fully
operational circuit with a few external components like one low-pass filter capacitor. The Input divider ratio (M) can be selected from a range of 1
to 2047, the output divider ratio (N) can be selected from a range of 1 to 4095 and they are set internally by using laser timing technologies.
Output frequency (fQ0) is equal to input clock frequency (f
CLKin
) multiplied by N/M. Output frequency range is 1MHz to 100MHz. Reference clock
from 8kHz to 36MHz can be input as the input clock. The IC stops operation and current drain is suppressed when a low level signal is input to the
CE pin which greatly reduces current consumption and produces a high impedance output.
The setting of the input divider ratio (M), output divider ratio (N), and charge pump current (Ip) are factory fixed semi-custom. Please advise your
Torex sales representative of your particular input/output frequency and supply voltage specifications so that we can see if we will be able to
support your requirements. The series is available in small SOT-26W and USP-6C.
APPLICATIONS
Clock for controlling a Imaging dot (LCD)
DSC (Digital still camera)
DVC (Digital video camera)
PND (Car navigation system)
UMPC (Ultra Mobile Personal Computer)
SSD (Solid State Disk)
Digital Photo Frame
Microcomputer and HDD drives
Cordless phones & Wireless communication
equipment
Various system clocks
■FEATURES
Input Frequency Range
Output Frequency Range
Output Divider (N) Range
Input Divider (M) Range
Operating Voltage Range
Low Power Consumption
Small Packages
: 8kHz ~ 36MHz
(*1)
: 1MHz ~ 100MHz
(f
Q0
=f
CLKin
× N/M)
(*1)
: 1 ~ 4095
(*1)
: 1 ~ 2047
(*1)
: 2.50V ~ 5.50V
(*1)
: 10μA MAX. when stand-by
(*2)
: SOT-26W, USP-6C
*1: The series are semi-custom products. Specifications for each
product are limited within the above range. The input frequency
range is set within ±5% of customer’s designated typical frequency.
Please note that setting of your some requirements may not be
possible due to the specification limits of this series.
*2: When the IC is in stand-by mode, the output becomes high impedance
and the IC stops operation.
■TYPICAL
APPLICATION CIRCUIT
TYPICAL PERFORMANCE
CHARACTERISTICS
PLL Output signal jitter 2 (t
J2
) (synchronous to an input signal)
XC25BS8001xx (610 multiplier, input 15kHz (TYP.))
*1
Input Signal
Output jitter
t
J2
=20(ns)
Output Signal
*1: C
IN
(by-pass capacitor, 0.1μF) and C1 ( LPF capacitor, 0.1μ
F) should be connected as close as possible to the IC. Please
refer to the pattern reference layout schematics on page 8 for
details.
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Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
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