5V19EE901PGGI datasheet, PDF - EEWORLD Datasheet

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5V19EE901PGGI: DescriptionTSSOP-28, Tube; Categorylogic logic; File Size515KB，36 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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5V19EE901PGGI Overview

TSSOP-28, Tube

5V19EE901PGGI Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	TSSOP
package instruction	0.173 MM, ROHS COMPLIANT, MO-153, TSSOP-28
Contacts	28
Manufacturer packaging code	PGG28
Reach Compliance Code	compliant
ECCN code	EAR99
series	5V
Input adjustment	MUX
JESD-30 code	R-PDSO-G28
JESD-609 code	e3
length	9.7 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Humidity sensitivity level	1
Number of functions	1
Number of inverted outputs
Number of terminals	28
Actual output times	7
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.075 ns
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	4.4 mm
minfmax	500 MHz
Base Number Matches	1

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DATASHEET

EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR

Description

The IDT5V19EE901 is a programmable clock generator

intended for high performance data-communications,

telecommunications, consumer, and networking

applications. There are four internal PLLs, each individually

programmable, allowing for four unique non-integer-related

frequencies. The frequencies are generated from a single

reference clock. The reference clock can come from one of

the two redundant clock inputs. Automatic or manual

switchover function allows any one of the redundant clocks

to be selected during normal operation.

The IDT5V19EE901 is in-system, programmable and can

be programmed through the use of I

C interface. An

internal EEPROM allows the user to save and restore the

configuration of the device without having to reprogram it on

power-up.

Each of the four PLLs has an 7-bit reference divider and a

12-bit feedback divider. This allows the user to generate

four unique non-integer-related frequencies. The PLL loop

bandwidth is programmable to allow the user to tailor the

PLL response to the application. For instance, the user can

tune the PLL parameters to minimize jitter generation or to

maximize jitter attenuation. Spread spectrum generation

and/or fractional divides are allowed on two of the PLLs.

There are a total of six 8-bit output dividers. Each output

bank can be configured to support LVTTL, LVPECL, LVDS

or HCSL logic levels. Out0 (Output 0) supports 3.3V single

ended output only. The outputs are connected to the PLLs

via a switch matrix. The switch matrix allows the user to

route the PLL outputs to any output bank. This feature can

be used to simplify and optimize the board layout. In

addition, each output's slew rate and enable/disable

function is programmable.

IDT5V19EE901

Features

•

Four internal PLLs

Internal non-volatile EEPROM

Fast (400kHz) mode I

C serial interface

Input frequency range: 1 MHz to 200 MHz

Output frequency range: 4.9 kHz to 500 MHz

Reference crystal input with programmable linear load

capacitance

– Crystal frequency range: 8 MHz to 50 MHz

(maximum crystal range is best effort)

•

Integrated VCXO

•

Each PLL has a 7-bit reference divider and a 12-bit

feedback-divider

•

8-bit output-divider blocks

•

Fractional division capability on one PLL

•

Two of the PLLs support spread spectrum generation

capability

•

I/O Standards:

– Outputs - 3.3 V LVTTL/ LVCMOS

– Outputs - LVPECL, LVDS and HCSL

– Inputs - 3.3 V LVTTL/ LVCMOS

•

Programmable slew rate control

Programmable loop bandwidth

Programmable output inversion to reduce bimodal jitter

Redundant clock inputs with auto and manual switchover

options

Individual output enable/disable

Power-down mode

3.3V core V

Available in TSSOP and VFQFPN packages

-40 to +85 C Industrial Temp operation

IDT®

EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR

IDT5V19EE901

REV R 092412

5V19EE901PGGI Related Products

	5V19EE901PGGI	5V19EE901NLGI
Description	TSSOP-28, Tube	VFQFPN-32, Tray
Brand Name	Integrated Device Technology	Integrated Device Technology
Is it lead-free?	Lead free	Lead free
Is it Rohs certified?	conform to	conform to
Parts packaging code	TSSOP	VFQFPN
package instruction	0.173 MM, ROHS COMPLIANT, MO-153, TSSOP-28	HVQCCN,
Contacts	28	32
Manufacturer packaging code	PGG28	NLG32P1
Reach Compliance Code	compliant	compliant
ECCN code	EAR99	EAR99
series	5V	5V
Input adjustment	MUX	MUX
JESD-30 code	R-PDSO-G28	S-XQCC-N32
JESD-609 code	e3	e3
length	9.7 mm	5 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
Humidity sensitivity level	1	3
Number of functions	1	1
Number of terminals	28	32
Actual output times	7	7
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Output characteristics	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	UNSPECIFIED
encapsulated code	TSSOP	HVQCCN
Package shape	RECTANGULAR	SQUARE
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260	260
Certification status	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.075 ns	0.075 ns
Maximum seat height	1.2 mm	0.9 mm
Maximum supply voltage (Vsup)	3.465 V	3.465 V
Minimum supply voltage (Vsup)	3.135 V	3.135 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V
surface mount	YES	YES
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed
Terminal form	GULL WING	NO LEAD
Terminal pitch	0.65 mm	0.5 mm
Terminal location	DUAL	QUAD
Maximum time at peak reflow temperature	30	30
width	4.4 mm	5 mm
minfmax	500 MHz	500 MHz
Base Number Matches	1	1

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