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FEATURES
Complete Dual Matching ADCs
Low Power Dissipation: 215 mW (+3 V Supply)
Single Supply: 2.7 V to 5.5 V
Differential Nonlinearity Error: 0.4 LSB
On-Chip Analog Input Buffers
On-Chip Reference
Signal-to-Noise Ratio: 57.8 dB
Over Nine Effective Bits
Spurious-Free Dynamic Range: –73 dB
No Missing Codes Guaranteed
28-Lead SSOP
Dual Channel, 20 MHz 10-Bit
Resolution CMOS ADC
AD9201
FUNCTIONAL BLOCK DIAGRAM
AVDD
IINA
IINB
IREFB
IREFT
QREFB
QREFT
VREF
REFSENSE
QINB
QINA
"Q" ADC
Q
REGISTER
REFERENCE
BUFFER
ASYNCHRONOUS
MULTIPLEXER
1V
CHIP
SELECT
THREE-
STATE
OUTPUT
BUFFER
DATA
10 BITS
AVSS
CLOCK
DVDD
DVSS
"I" ADC
I
REGISTER
AD9201
SLEEP
SELECT
PRODUCT DESCRIPTION
PRODUCT HIGHLIGHTS
The AD9201 is a complete dual channel, 20 MSPS, 10-bit
CMOS ADC. The AD9201 is optimized specifically for applica-
tions where close matching between two ADCs is required (e.g.,
I/Q channels in communications applications). The 20 MHz
sampling rate and wide input bandwidth will cover both narrow-
band and spread-spectrum channels. The AD9201 integrates two
10-bit, 20 MSPS ADCs, two input buffer amplifiers, an internal
voltage reference and multiplexed digital output buffers.
Each ADC incorporates a simultaneous sampling sample-and-
hold amplifier at its input. The analog inputs are buffered; no
external input buffer op amp will be required in most applica-
tions. The ADCs are implemented using a multistage pipeline
architecture that offers accurate performance and guarantees no
missing codes. The outputs of the ADCs are ported to a multi-
plexed digital output buffer.
The AD9201 is manufactured on an advanced low cost CMOS
process, operates from a single supply from 2.7 V to 5.5 V, and
consumes 215 mW of power (on 3 V supply). The AD9201 input
structure accepts either single-ended or differential signals,
providing excellent dynamic performance up to and beyond
its 10 MHz Nyquist input frequencies.
1. Dual 10-Bit, 20 MSPS ADCs
A pair of high performance 20 MSPS ADCs that are opti-
mized for spurious free dynamic performance are provided for
encoding of I and Q or diversity channel information.
2. Low Power
Complete CMOS Dual ADC function consumes a low
215 mW on a single supply (on 3 V supply). The AD9201
operates on supply voltages from 2.7 V to 5.5 V.
3. On-Chip Voltage Reference
The AD9201 includes an on-chip compensated bandgap
voltage reference pin programmable for 1 V or 2 V.
4. On-chip analog input buffers eliminate the need for external
op amps in most applications.
5. Single 10-Bit Digital Output Bus
The AD9201 ADC outputs are interleaved onto a single
output bus saving board space and digital pin count.
6. Small Package
The AD9201 offers the complete integrated function in a
compact 28-lead SSOP package.
7. Product Family
The AD9201 dual ADC is pin compatible with a dual 8-bit
ADC (AD9281) and has a companion dual DAC product,
the AD9761 dual DAC.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
AD9201–SPECIFICATIONS
Parameter
RESOLUTION
CONVERSION RATE
DC ACCURACY
Differential Nonlinearity
Integral Nonlinearity
Differential Nonlinearity (SE)
Integral Nonlinearity (SE)
Zero-Scale Error, Offset Error
Full-Scale Error, Gain Error
Gain Match
Offset Match
ANALOG INPUT
Input Voltage Range
Input Capacitance
Aperture Delay
Aperture Uncertainty (Jitter)
Aperture Delay Match
Input Bandwidth (–3 dB)
Small Signal (–20 dB)
Full Power (0 dB)
INTERNAL REFERENCE
Output Voltage (1 V Mode)
Output Voltage Tolerance (1 V Mode)
Output Voltage (2 V Mode)
Output Voltage Tolerance (2 V Mode)
Load Regulation (1 V Mode)
Load Regulation (2 V Mode)
POWER SUPPLY
Operating Voltage
Supply Current
Power Consumption
Power-Down
Power Supply Rejection
DYNAMIC PERFORMANCE
1
Signal-to-Noise and Distortion
f = 3.58 MHz
f = 10 MHz
Signal-to-Noise
f = 3.58 MHz
f = 10 MHz
Total Harmonic Distortion
f = 3.58 MHz
f = 10 MHz
Spurious Free Dynamic Range
f = 3.58 MHz
f = 10 MHz
Two-Tone Intermodulation Distortion
2
Differential Phase
Differential Gain
Crosstalk Rejection
F
S
DNL
INL
DNL
INL
E
ZS
E
FS
Symbol
(AVDD = +3 V, DVDD = +3 V, F
SAMPLE
= 20 MSPS, VREF = 2 V, INB = 0.5 V, T
MIN
to T
MAX,
internal ref, differential input signal, unless otherwise noted)
Min
Typ
10
20
±
0.4
1.2
±
0.5
±
1.5
±
1.5
±
3.5
±
0.5
±
5
–0.5
2
4
2
2
240
245
Max
Units
Bits
MHz
LSB
LSB
LSB
LSB
% FS
% FS
LSB
LSB
V
pF
ns
ps
ps
MHz
MHz
V
mV
V
mV
mV
mV
V
V
mA
mA
mW
mW
% FS
REFSENSE = VREF
REFSENSE = GND
1 mA Load Current
1 mA Load Current
AVDD – DVDD
≤
2.3 V
AVDD = 3 V
AVDD = DVDD = 3 V
STBY = AVDD, Clock = AVSS
REFT = 1 V, REFB = 0 V
REFT = 1 V, REFB = 0 V
Condition
±
1
±
2.5
±
3.8
±
5.4
AIN
C
IN
t
AP
t
AJ
BW
AVDD/2
VREF
VREF
1
±
10
2
±
15
±
15
±
28
AVDD
DRVDD
I
AVDD
I
DRVDD
P
D
PSR
SINAD
2.7
2.7
3
3
71.6
0.1
215
15.5
0.8
5.5
5.5
245
1.3
55.6
SNR
55.9
THD
57.3
55.8
57.8
56.2
–69
–66.3
–63.3
dB
dB
dB
dB
dB
dB
dB
dB
dB
Degree
%
dB
SFDR
–66
IMD
DP
DG
–73
–70.5
–62
0.1
0.05
68
f = 44.49 MHz and 45.52 MHz
NTSC 40 IRE Mod Ramp
F
S
= 14.3 MHz
–2–
REV. D
AD9201
Parameter
DYNAMIC PERFORMANCE (SE)
3
Signal-to-Noise and Distortion
f = 3.58 MHz
Signal-to-Noise
f = 3.58 MHz
Total Harmonic Distortion
f = 3.58 MHz
Spurious Free Dynamic Range
f = 3.58 MHz
DIGITAL INPUTS
High Input Voltage
Low Input Voltage
DC Leakage Current
Input Capacitance
LOGIC OUTPUT (with DVDD = 3 V)
High Level Output Voltage
(I
OH
= 50
µA)
Low Level Output Voltage
(I
OL
= 1.5 mA)
LOGIC OUTPUT (with DVDD = 5 V)
High Level Output Voltage
(I
OH
= 50
µA)
Low Level Output Voltage
(I
OL
= 1.5 mA)
Data Valid Delay
MUX Select Delay
Data Enable Delay
Data High-Z Delay
CLOCKING
Clock Pulsewidth High
Clock Pulsewidth Low
Pipeline Latency
NOTES
1
AIN differential 2 V p-p, REFT = 1.5 V, REFB = –0.5 V.
2
IMD referred to larger of two input signals.
3
SE is single ended input, REFT = 1.5 V, REFB = –0.5 V.
Specifications subject to change without notice.
t
OD
Symbol
SINAD
Min
Typ
Max
Units
Condition
52.3
SNR
55.5
THD
–55
SFDR
–58
V
IH
V
IL
I
IN
C
IN
2.4
±
6
2
0.3
dB
dB
dB
dB
V
V
µA
pF
V
OH
V
OL
2.88
0.095
V
V
V
OH
V
OL
t
OD
t
MD
t
ED
t
DHZ
t
CH
t
CL
22.5
22.5
4.5
0.4
11
7
13
13
V
V
ns
ns
ns
ns
ns
ns
Cycles
C
L
= 20 pF. Output Level to
90% of Final Value
3.0
CLOCK
INPUT
ADC SAMPLE
#1
ADC SAMPLE
#2
ADC SAMPLE
#3
ADC SAMPLE
#4
ADC SAMPLE
#5
SELECT
INPUT
Q CHANNEL
OUTPUT ENABLED
t
MD
I CHANNEL
OUTPUT ENABLED
SAMPLE #1
Q CHANNEL
OUTPUT
SAMPLE #2
Q CHANNEL
OUTPUT
SAMPLE #1-1
Q CHANNEL
OUTPUT
DATA
OUTPUT
SAMPLE #1-3
Q CHANNEL
OUTPUT
SAMPLE #1-2
Q CHANNEL
OUTPUT
SAMPLE #1-1
I CHANNEL
OUTPUT
SAMPLE #1
I CHANNEL
OUTPUT
Figure 1. ADC Timing
REV. D
–3–
AD9201
ABSOLUTE MAXIMUM RATINGS*
PIN FUNCTION DESCRIPTIONS
Parameter
With
Respect
to
P
in
Min
–0.3
–0.3
–0.3
–6.5
–0.3
–0.3
–1.0
–0.3
–0.3
–0.3
–65
Max
+6.5
+6.5
+0.3
+6.5
AVDD + 0.3
DVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
+150
+150
+300
Units
V
V
V
V
V
V
V
V
V
V
°C
°C
°C
No.
1
2
3
4
5
6
7
8
9
10
11
12
Name
DVSS
DVDD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
Description
Digital Ground
Digital Supply
Bit 0 (LSB)
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9 (MSB)
AVDD
AVSS
DVDD
DVSS
AVSS
DVSS
AVDD
DVDD
CLK
AVSS
Digital Outputs
DVSS
AINA, AINB
AVSS
VREF
AVSS
REFSENSE
AVSS
REFT, REFB
AVSS
Junction Temperature
Storage Temperature
Lead Temperature
10 sec
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SELECT
CLOCK
SLEEP
INA-I
INB-I
REFT-I
REFB-I
AVSS
REFSENSE
VREF
AVDD
REFB-Q
REFT-Q
INB-Q
INA-Q
CHIP-SELECT
Hi I Channel Out, Lo Q Channel Out
Clock
Hi Power Down, Lo Normal Operation
I Channel, A Input
I Channel, B Input
Top Reference Decoupling, I Channel
Bottom Reference Decoupling, I Channel
Analog Ground
Reference Select
Internal Reference Output
Analog Supply
Bottom Reference Decoupling, Q Channel
Top Reference Decoupling, Q Channel
Q Channel, B Input
Q Channel, A Input
Hi-High Impedance, Lo-Normal Operation
ORDERING GUIDE
Temperature
Range
–40°C to +85°C
Package
Description
Package
Options*
Model
AD9201ARS
AD9201-EVAL
28-Lead SSOP
RS-28
Evaluation Board
*RS = Shrink Small Outline.
PIN CONFIGURATION
DVSS
DVDD
(LSB) D0
D1
D2
D3
D4
D5
D6
D7
D8
(MSB) D9
SELECT
CLOCK
CHIP-SELECT
INA-Q
INB-Q
REFT-Q
AD9201
TOP VIEW
(Not to Scale)
REFB-Q
AVDD
VREF
REFSENSE
AVSS
REFB-I
REFT-I
INB-I
INA-I
SLEEP
DEFINITIONS OF SPECIFICATIONS
INTEGRAL NONLINEARITY (INL)
Integral nonlinearity refers to the deviation of each individual
code from a line drawn from “zero” through “full scale.” The
point used as “zero” occurs 1/2 LSB before the first code tran-
sition. “Full scale” is defined as a level 1 1/2 LSBs beyond the
last code transition. The deviation is measured from the center
of each particular code to the true straight line.
DIFFERENTIAL NONLINEARITY (DNL, NO MISSING
CODES)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. It is often
specified in terms of the resolution for which no missing codes
(NMC) are guaranteed.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9201 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. D
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