Application Note
AN1794/D
Rev. 0.1, 11/2001
Backside L2 Timing Analysis
for PCB Design Engineers
Bruce Parker
risc10
@email.sps.mot.com
The backside L2 interfaces on the MPC750 and the G4 processors dramatically increase their
performance. Since the L2 design basically connects the processor’s L2 controller to the
memory SRAMs, the main task for the board designer is to determine what board propagation
delays will provide sufficient setup and hold margins for a given target frequency. This
document discusses how to determine the propagation delay restrictions for the backside L2
interface of processors that implement the PowerPC architecture and a method for optimizing
the setup and hold margins by using clock offsets.
Setup and hold margins are controlled partially by the processor and memory timing
specifications, and partially by the PCB propagation and skew characteristics. Using the
various timing specifications from the processor and memory data sheets, one can calculate
the minimum and maximum propagation delay allowable. Once these delays are known for all
cycle types (that is, address, data write, and data read cycles) one can optimize the setup and
hold margins by adding delay to either the processor’s L2 feedback clock or to the memory’s
clock. Once an offset, if any, is calculated, the final allowable propagation delays can be
converted to length restrictions for use by the PCB layout designer.
The following definitions are used during the analysis:
•
•
•
•
•
•
t
co_src
—Time from the rising edge of the clock until the output becomes valid;
specified by the source of the output signal
t
oh_src
—Time from the rising edge of the clock until the output becomes invalid;
specified by the source of the output signal
t
su_rcvr
—Time that an input must be valid before the rising edge of the clock;
specified by the receiver of the signal
t
ih_rcvr
—Time that an input must remain valid after the rising edge of the clock;
specified by the receiver of the signal
t
jitter
—Clock jitter from L2 clock source (cycle-to-cycle)
t
cksk
—Clock skew introduced from PCB routing and clock loading differences; this
includes unintentional length mismatches, skew from PCB impedance differences,
and skew due to clock loading differences.
t
per
—Clock period of L2 interface
t
prop
—Time for a signal to propagate from a driver’s output to a receiver’s input
t
ckoffset
—An intentional offset between the L2 controller’s feedback clock and the
memory’s clock. This offset is calculated later in this document.
•
•
•
Procedure and Analysis
1.1
Procedure and Analysis
The initial analysis is just a typical timing analysis used to calculate setup and hold margins. The L2
feedback clock is assumed to be equal in length to the memory clock length, thus both the processor’s L2
controller and the memory devices clock signals in and out at the same instance in time. The second part of
this analysis investigates how offsetting the clocks can optimize timing margins.
The equations below are used to calculate the minimum and maximum propagation delays. For the L2
interface, the analysis must consider both address and data cycles. From a propagation delay calculation
viewpoint, an address cycle and a data write cycle have the same equation since the L2 controller has the
same timing specifications for address and data outputs.
1.2
Setup Time Margin and Maximum
Propagation Delays
t
su_margin
= t
per
- t
su_total
(EQ 1)
The setup margin can be defined as the difference between the clock period, (t
per
), and the total setup time,
t
su_total
, as shown below:
The total setup time is the accumulation of the driver’s clock to output valid (t
co_src
), the receiver’s input
setup (t
su_rcvr
), the L2 controller’s clock jitter, t
jitter
, the PCB clock skew, t
cksk
, and the propagation delay of
the signal being analyzed which results in:
t
su_total
=
t
cksk
+
t
su_rcvr
+
t
jitter
+
t
cksk
+
t
prop_max
(EQ 2)
By substituting for t
su_total
from EQ. 1, and solving for t
prop_max
from EQ. 2, the formula for calculating the
maximum allowable propagation delay is:
t
prop_max
=
t
per
- t
co_src
- t
su_rcvr
- t
jitter
- t
cksk
- t
su_margin
(EQ 3)
This propagation delay is used to determine the maximum net length restriction for a given signal group to
meet setup time specifications.
1.3
Hold Time Margin and Minimum
Propagation Delays
The hold time margin can be defined as the driver’s output hold time (t
oh_src
), minus the receiver’s input hold
(t
ih_rcvr
), plus the minimum propagation delay (
t
prop_min
). The worst case hold margin must also subtract out
the clock jitter (t
jitter
) and the clock skew (t
cksk
), as shown:
t
ho_margin
=
t
oh_src
-
t
ih_rcvr
+ t
prop_min
-
t
jitter
-
t
cksk
t
prop_min =
t
ih_rcvr -
t
oh_src
+
t
ho_margin
+
t
jitter
+
t
cksk
(EQ 4)
Solving for the propagation delay, the formula for calculating the minimum allowable propagation delay is:
(EQ 5)
This propagation delay is used to determine the minimum net length restriction for a given signal group to
meet hold time specifications. An important note is that the hold time margin is not directly frequency
dependent. It will vary with frequency if the hold time specifications for either the driver or receiver vary
with frequency.
2
Backside L2 Timing Analysis for PCB Design Engineers
MOTOROLA
Analysis and Clock Offsets
1.4
Analysis and Clock Offsets
One can now plug in the numbers from the processor and memory data sheets to find the maximum and
minimum propagation delays for each signal group. For the backside L2 interface the signals can be grouped
into two signal groups, address and data. Since the data bus is bidirectional, timing margins for both reads
and writes must be considered. However, the signal source is the processor for both address cycles and data
write cycles. Since all outputs from the processor’s L2 interface have the same timing specifications, this
analysis will consider an address cycle to require the same propagation delays as a data write cycle. When
converting from propagation delay time to length restrictions, other factors such as loading and routing
topology must be considered.
So, there are two cycle types whose propagation delays must be calculated and analyzed. First is the address
cycle, where the processor is the source and the memory is the receiver. Second is the data read cycle, where
the memory device is the source and the processor is the receiver. For each cycle type the equations will
provide a minimum and maximum propagation delay for any given frequency. This is essentially a range of
allowable propagation delays. The range can be plotted on a time-line graph to compare the ranges of the
different cycle types as shown in Figure 1. The data write cycle is shown for clarity, but is just the same as
the address cycle range. Unless the processor and memory have the same timing specifications, the ranges
will be different for the different cycle types.
Address
Minimum
Propagation
Time
Data
Data Write
Maximum
Propagation
Time
Data Read
-3
-2
-1
0
1
2
3
ns
Figure 1. Propagation Delay Time-line Graph
Once the ranges are plotted, they can be analyzed to determine if there is a need to shift the ranges by using
clock offsets. As shown in Figure 1, the left side of a range represents the minimum propagation delay while
the right side represents the maximum propagation delay for that cycle type. Notice the data signal group
has two cycle types—data write and data read. The actual range allowed for a data signal is the overlap of
the data write and data read ranges.
For the initial analysis, it was assumed the L2 feedback clock and the memory clocks were aligned in time,
therefore the intentional clock offset (t
ckoffset
) was 0 ns. By introducing clock offsets between the L2
feedback clock and the memory clock, the ranges can be shifted to optimize the propagation delays, and
thus the setup and hold margins. If additional trace is added to the L2 feedback clock, the address (and data
write) range will shift to the left and the data read range will shift to the right as shown in Figure 2. If
additional trace is added to the memory clock, the address (and data write) range will shift to the right and
the data read range will shift to the left. The ranges will shift an amount equal to the delay introduced by the
additional trace. The delay calculation is covered in the example in “Calculating the Length” on page 6.
MOTOROLA
Backside L2 Timing Analysis for PCB Design Engineers
3
An Example
Address before
clock offset
Address after
clock offset
Data Write after
clock offset
Data after
clock offset
Data Read after
clock offset
Data Read before
clock offset
-3
-2
-1
0
1
2
3
ns
Figure 2. Propagation Delay Time-line Graph with Clock Offset
1.5
An Example
To illustrate the concepts presented here, an example is analyzed. This example will use a Motorola G4
processor with two Motorola MCM69P737 memories. The G4 is a next generation of processors that
implement the PowerPC architecture with backside L2 support, while the MCM69P737 is a 128Kx36 bit
pipelined, burst SRAM. From the data sheets, one first creates Table 1.
Table 1. Specifications from Device Data Sheets
Specification
t
co
t
oh
t
su
t
ih
t
jitter
load-cap
Processor
2.5
0.4
1.5
0.0
150
7.0
Memory
3.0
1.5
1.2
0.4
n/a
7.0
Units
ns
ns
ns
ns
ps
pf
For this example the PCB clock skew (t
cksk
) used is 0.020 ns. Using Table 1. and the equations for the
minimum and maximum propagation delay from the previous sections we create Figure 2 for three different
frequencies.
4
Backside L2 Timing Analysis for PCB Design Engineers
MOTOROLA
An Example
Table 2. Propagation Delays with No Clock Offsets
Address or Data Write
L2 Freq (MHz)
150
175
200
Data Read
t
prop_min (ns)
-1.330
-1.330
-1.330
t
prop_max (ns)
1.997
1.044
0.330
t
ckoffset (ns)
0.000
0.000
0.000
t
prop_min (ns)
0.170
0.170
0.170
t
prop_max (ns)
2.797
1.844
1.130
In creating Figure 2, the setup and hold margins are set to 0 for this example. This implies the results
represent the maximum and minimum propagation delays with 0 ns of setup and hold margin. However, any
negative minimum propagation delay translates directly into hold margin, since no trace can have negative
propagation delay time. The actual hold margin will be any negative minimum propagation delay from the
final table, plus the trace delay of the shortest signal in a given signal group. From Figure 2 we can create
the time-line for any of the frequencies. The time-line for 200 MHz is shown in Figure 3.
Address
Data Write
Data
Data Read
-2
-1
0
1
2
ns
Figure 3. Propagation Delay Time-line for 200 MHz with no Clock Offset
As shown in Figure 3, the data range appears severely restricted due to the small overlap between a data
write cycle and a data read cycle. By adding delay to the L2 feedback clock, we can shift the address (and
data write) window left and the data read window right. How much to shift the windows depends on the
relative length of the longest data trace to the longest address trace. This ratio will be dependent on package
types and PCB placement. For this example, the longest data trace is approximately 75% the length of the
longest address trace. Once a percentage is chosen, the clock offset to achieve this percentage is calculated
with the following equation:
t
ckoffset
= ((percentage * t
prop_max
addr) - t
prop_max
data) / (1 + percentage)
(EQ 6)
where the percentage is expressed as a decimal number (that is, 75% is 0.75). Using this equation and
Table 2, we calculate the new clock offset. Once the clock offset is known, the equations for propagation
delays (EQ 3 and EQ 5) are modified to account for the clock offset as shown below:
t
prop
_max
=
t
per
-
t
co_src
-
t
su_rcvr
-
t
jitter
-
t
cksk
-
t
su_margin
-
t
ckoffset
t
prop_min =
t
ih_rcvr -
t
oh_src
+
t
ho_margin
+
t
jitter
+
t
cksk
-
t
ckoffset
(EQ 7)
(EQ 8)
MOTOROLA
Backside L2 Timing Analysis for PCB Design Engineers
5
京公网安备 11010802033920号
EEWORLD
