74LVTH573MSAX datasheet, PDF - EEWORLD Datasheet

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74LVTH573MSAX: DescriptionOctal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-PDIP -40 to 85; Categorylogic logic; File Size106KB，8 Pages; ManufacturerFairchild; Websitehttp://www.fairchildsemi.com/; Environmental Compliance

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74LVTH573MSAX Overview

Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-PDIP -40 to 85

74LVTH573MSAX Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Fairchild
Parts packaging code	SSOP
package instruction	SSOP, SSOP20,.3
Contacts	20
Reach Compliance Code	compliant
Other features	BROADSIDE VERSION OF 373
series	LVT
JESD-30 code	R-PDSO-G20
JESD-609 code	e3
length	7.2 mm
Logic integrated circuit type	BUS DRIVER
MaximumI(ol)	0.064 A
Humidity sensitivity level	1
Number of digits	8
Number of functions	1
Number of ports	2
Number of terminals	20
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	SSOP
Encapsulate equivalent code	SSOP20,.3
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH
method of packing	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Prop。Delay @ Nom-Sup	4.4 ns
propagation delay (tpd)	5 ns
Certification status	Not Qualified
Maximum seat height	2.05 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	BICMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	5.3 mm
Base Number Matches	1

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74LVT573 • 74LVTH573 Low Voltage Octal Transparent Latch with 3-STATE Outputs

March 1999

Revised March 2005

74LVT573 • 74LVTH573

Low Voltage Octal Transparent Latch

with 3-STATE Outputs

General Description

The LVT573 and LVTH573 consist of eight latches with

3-STATE outputs for bus organized system applications.

The latches appear transparent to the data when Latch

Enable (LE) is HIGH. When LE is low, the data satisfying

the input timing requirements is latched. Data appears on

the bus when the Output Enable (OE) is LOW. When OE is

HIGH, the bus output is in the high impedance state.

The LVTH573 data inputs include bushold, eliminating the

need for external pull-up resistors to hold unused inputs.

These octal latches are designed for low-voltage (3.3V)

applications, but with the capability to provide a TTL

interface to a 5V environment. The LVT573 and LVTH573

are fabricated with an advanced BiCMOS technology to

achieve high speed operation similar to 5V ABT while

maintaining a low power dissipation.

Features

Input and output interface capability to systems at

5V V

Bushold data inputs eliminate the need for external

pull-up resistors to hold unused inputs (74LVTH573),

also available without bushold feature (74LVT573)

Live insertion/extraction permitted

Power Up/Down high impedance provides glitch-free

bus loading

Outputs source/sink

32 mA/

64 mA

Functionally compatible with the 74 series 573

Latch-up performance exceeds 500 mA

ESD performance:

Human-body model

2000V

Machine model

200V

Charged-device model

1000V

Ordering Code:

Order Number

74LVT573WM

74LVT573SJ

74LVT573MSA

74LVT573MTC

74LVT573MTCX_NL

(Note 1)

74LVTH573WM

74LVTH573SJ

74LVTH573MSA

74LVTH573MTC

74LVTH573MTCX_NL

(Note 1)

Package

Number

M20B

M20D

MSA20

MTC20

M20B

M20D

MSA20

MTC20

Package Description

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Pb-Free package per JEDEC J-STD-020B.

Note 1:

“_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.

DS012450

www.fairchildsemi.com

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