HM 65797
256 K x 1 High Speed CMOS SRAM
Introduction
The HM 65797 is a high speed CMOS static RAM
organized as 262, 144
×
1 bit. It is manufactured using
MHS high performance CMOS technology.
Access times as fast 20ns are available with maximum
power consumption of only 770 mW.
The HM 65797 features fully static operation requiring no
external clocks or timing strobes. The automatic
power-down feature reduces the power consumption by
67 % when the circuit is deselected.
Easy memory expansion is provided by an active low chip
select (CS) and three state drivers.
All inputs and outputs of the HM 65797 are TTL
compatible and operate from single 5 V supply thus
simplifying system design.
The HM 65797 is 100 % processed following the test
methods of MIL STD 883 and/or ESA/SCC 9000 making
it ideally suitable for military/space applications that
demand superior levels of performance and reliability.
Features
D
Fast access time
Commercial/industrial : 20/25/35/45/55 ns (max)
Military : 25/35/45/55 ns (max)
D
Low power consumption
Active : 770 mW
Standby : 220 mW
D
Wide temperature range :
–55°C to + 125°C
D
300 mils width package
D
TTL compatible inputs and outputs asynchronous
D
Capable of withstanding greater than 2000V electrostatic
discharge single 5 volt supply
Interface
Block Diagram
MATRA MHS
Rev. D (16 April.97)
1
Preliminary Information
HM 65797
Pin Configuration
Plastic 300 mils, 24 pins, DIL
Ceramic 300 mils, 24 pins, DIL
Pinout DIL/SO 24 pins (top view)
Pin Names
A0–A13: Address inputs
Din
Dout
CS
: Input
: Output
: Chip Select
W
Vcc
GND
: Write enable
: Power
: Ground
Truth Table
CS
H
L
L
W
X
H
L
INPUT
Z
Z
Valid
OUTPUT
Z
Valid
Z
MODE
Deselect
Read
Write
L = Low – H = High, X = H or L, Z = High impedance.
Electrical Characteristics
Absolute Maximum Ratings
Supply voltage to GND potential : . . . . . . . . . . . . . . . –0.5 V to +7.0 V
DC input voltage : . . . . . . . . . . . . . . . . . . . . . . . . . . . –3.0 V to +7.0 V
DC output voltage in high Z state : . . . . . . . . . . . . . . –0.5 V to +7.0 V
Storage temperature : . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Output current into outputs (low) : . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Electro Static Discharge Voltage . . . . . . . . . . . . . . . . . . . . . . > 2000 V
(MIL STD 883C METHOD 3015-5)
Operating Range
OPERATING VOLTAGE
Military
Industrial
Commercial
(– 2)
(– 9)
(– 5)
5 V
±
10 %
5 V
±
10 %
5 V
±
10 %
OPERATING TEMPERATURE
– 55_C to + 125_C
– 40_C to + 85_C
– 0_C to + 70_C
Recommended DC Operating Conditions
PARAMETER
Vcc
Gnd
VIL
VIH
DESCRIPTION
Supply Voltage
Ground
Input low voltage
Input high voltage
MINIMUM
4.5
0.0
– 3.0
2.2
TYPICAL
5.0
0.0
0.0
–
MAXIMUM
5.5
0.0
0.8
VCC
UNIT
V
V
V
V
2
MATRA MHS
Rev. D (16 April.97)
Preliminary Information
HM 65797
Capacitance
PARAMETER
Cin
Cout
Note :
(1)
(1)
DESCRIPTION
Input capacitance
Output capacitance
MINIMUM
–
–
TYPICAL
–
–
MAXIMUM
5
7
UNIT
pF
pF
1. TA = 25°C, f = 1 MHz, Vcc = 5.0 V, these parameters are not tested.
AC Test Loads and Waveforms
Figure 1
a
Equivalent to : THEVENIN EQUIVALENT
Figure 1 b
Figure 2
Commercial
Military
DC Parameters
PARAMETER
IIX
IOZ
IOS
VOL
VOH
Note :
(2)
(3)
(4)
(5)
(2)
DESCRIPTION
Input leakage current
Output leakage current
Output short circuit current
Output low voltage
Output high voltage
MINIMUM
– 10.0
– 10.0
–
–
2.4
TYPICAL
–
–
–
–
–
MAXIMUM
10.0
10.0
– 350.0
0.4
–
UNIT
µA
µA
mA
V
V
2. Gnd < Vin < Vcc, Gnd < Vout < Vcc Output disabled.
3. Vcc = max, Vout = Gnd, duration of the short circuit should not exceed 30 seconds.
Not more than 1 output should be shorted at one time.
4. Vcc min, IOL = 8.0 mA (military), IOL = 12.0 mA (commercial).
5. Vcc min, IOH = –4.0 mA.
MATRA MHS
Rev. D (16 April.97)
3
Preliminary Information
HM 65797
Consumption for Commercial (–5) Specification
SYMBOL
ICCSB
ICCSB1
ICCOP
(6)
(8)
(7)
PARAMETER
Standby supply current
Standby supply current
Dynamic operating current
65797
F–5
40
20
140
65797
H–5
35
20
100
65797
K–5
35
20
100
65797
M–5
35
20
100
65797
N–5
35
20
100
UNIT
mA
mA
mA
VALUE
max
max
max
Consumption for Industrial (–9) and Military (–2) Specification
SYMBOL
ICCSB
ICCSB1
ICCOP
Note :
(6)
(8)
(7)
PARAMETER
Standby supply current
Standby supply current
Dynamic operating current
65797
F–9
40
20
150
65797
H–9/–2
35
20
110
65797
K–9/–2
35
20
110
65797
M–9/–2
35
20
110
65797
N–9/–2
35
20
110
UNIT
mA
mA
mA
VALUE
max
max
max
6. CS
≥
VIH, a pull-up resistor to Vcc on the CS is required to keep the device unselected during the Vcc power-up. Otherwise
IccSB will exceed the above values. Min duty cycle = 100 %.
7. Vcc max, Output current = 0 mA, f = max, Vin = Vcc or Gnd.
8. CS
≥
Vcc – 0.3 V Iout = 0 mA.
AC Parameters
Input pulse levels : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gnd to 3.0 V
Input rise : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns
Input timing reference levels : . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output loading IOL/IOH
(see figure 1a and 1b)
: . . . . . . . . . . . +30 pF
Write Cycle Specification : Commercial, Industrial and Military
SYMBOL
TAVAV
TAVWL
TAVWH
TDVWH
TELWH
TWLQZ(9)
TWLWH
TWHAX
TWHDX
TWHQX
Note :
(9)
PARAMETER
Write cycle time
Address set–up time
Address valid to end to write
Data set–up time
CS low to write end
Write low to high Z
Write pulse width
Address hold from write end
Data hold time
Write high to low Z
65797
F–5/–9
20
0
15
10
15
10
15
0
0
3
65797
H–5/–9
/–2
25
0
20
15
20
13
20
0
0
3
65797
K–5/–9
/–2
35
0
30
17
30
15
25
0
0
3
65797
M–5/–9
/–2
45
0
40
20
40
20
30
0
0
3
65797
N–5/–9
/–2
55
0
50
25
50
25
35
0
0
3
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
VALUE
min
min
min
min
min
max
min
min
min
min
9. The data input set-up and hold timing should be referenced to rising edge of the signal that terminates the write.
4
MATRA MHS
Rev. D (16 April.97)
Preliminary Information
HM 65797
Write Cycle 1 : W Controlled (note 10)
Write Cycle 2 : CS controlled (note 10)
Note :
10. The internal write of the memory is defined by the overlap of CS LOW and W LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input setup and hold timing should be referenced to rising edge of the signal that
terminates the write.
MATRA MHS
Rev. D (16 April.97)
5
Preliminary Information
Test/Measurement
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