512K x 8 SRAM
MSM8512 - 70/85/10
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (619) 674 2233, Fax No: (619) 674 2230
Issue 4.3 : January 1999
Description
The MSM8512 is a 4Mbit monolithic SRAM
organised as 512K x 8 with access times from
70ns to 100ns available. The device is available in
three 32 pin ceramic packages, one being the
space saving VIL
TM
. The device has a low power
standby version which supports data retention
mode and is directly TTL compatible.
All versions can be screened in accordance with
MIL-STD-883C.
524,288 x 8 CMOS Static RAM
Features
Fast Access Times of 70/85/100 ns
JEDEC standard package.
Average Operating Power 385 mW (max)
Standby Power
550
µW
(max) -L version
Low voltage data retention.
Completely Static Operation
Directly TTL compatible
May be processed in accordance with MIL-STD-883C
Block Diagram
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
D0
D7
WE
OE
CS
Pin Definition
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D0
A0
A1
A2
A3
A4
A5
A6
A7
32
31
30
29
28
27
4,194,304
BIT
MEMORY
ARRAY
S,V
Package
Top View
26
25
24
23
22
21
20
19
18
17
I/O
BUFFER
COLUMN I/O
COLUMN DECODE
Y ADDRESS BUFFER
Vcc
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
D7
D6
D5
D4
D3
X ADDRESS BUFFER
ROW DECODE
13
12
11
10
9
8
7
6
5
D1
D2
GND
D3
D4
D5
D6
Package Details
Pin Count
32
32
32
Descripion
Package Type
S
V
J
0.6" Dual-in-Line (DIP)
0.1" Vertical-in-line (VIL
TM
)
Extended JLCC Package
Pin Functions
A0-A18
Address Inputs
D0-7
Data Input/Output
CS
Chip Select
OE
Output Enable
WE
Write Enable
Power (+5V)
V
CC
GND
Ground
A17
A10
OE
A11
A9
A8
A13
WE
D7
21
22
23
24
25
26
27
28
29
14
15
16
17
18
19
20
A8
A7
A6
A5
A4
A3
A2
A1
A0
TOP VIEW
J
4
3
2
1
32
31
30
A12
A14
A16
A18
VCC
A15
CS2
ISSUE 4.3 : January 1999
MSM8512 - 70/85/10
DC OPERATING CONDITIONS
Absolute Maximum Ratings
(1)
Voltage on any pin relative to V
SS (2)
Power Dissipation
Storage Temperature
V
T
P
T
T
STG
-0.5
-55
to
1
to
+7.0
+150
V
W
O
C
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
(2) Pulse width:- 3.0V for less than 30ns.
Recommended Operating Conditions
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
Symbol
V
CC
V
IH
V
IL
T
A
T
AI
T
AM
min
4.5
2.2
-0.3
0
-40
-55
typ
5.0
-
-
-
-
-
max
5.5
6.0
0.8
70
85
125
unit
V
V
V
o
C
o
C
o
C
(I suffix)
(M, MB suffix)
DC Electrical Characteristics
(V
CC
= 5.0V±10%, T
A
=-55°C to +125°C)
Parameter
Input Leakage Current
Output Leakage Current
Average Supply Current
Standby Supply Current
-L version only
Output Voltage
Symbol Test Condition
I
LI
I
LO
I
CC1
I
SB
I
SB1
V
OL
V
OH
V
IN
=0V to V
CC
CS=V
IH
, V
I/O
=0V to V
CC
, OE=V
IH
or WE=V
IL
CS=V
IL
, I
I/O
=0mA, min cycle, duty=100%
CS=V
IH
, V
IN
=V
IH
or V
IL
CS
≥
V
CC
-0.2V, V
IN
≥
V
CC
-0.2V or 0.2V
≥
V
IN
I
OL
=2.1mA
I
OH
=-1.0mA
min
-1
-1
-
-
-
typ
-
-
-
-
-
-
-
max
1
1
70
3
100
0.4
-
Unit
µA
µA
mA
mA
µA
V
V
-
2.4
Capacitance
(V
CC
=5V±10%,T
A
=25°C)
Parameter
Input Capacitance:
I/O Capacitance:
Symbol
C
IN
C
I/O
Test Condition
V
IN
= 0V
V
I/O
= 0V
typ
-
-
max
8
10
Unit
pF
pF
Note : This parameter is sampled and not 100% tested.
AC Test Conditions
* Input pulse levels: 0.8V to 2.2V
* Input rise and fall times: 5ns
* Input and Output timing reference levels: 1.5V
* Output load: See Load Diagram
* V
cc
=5V±10%
Output Load
I/O Pin
645
Ω
1.76V
100pF
2
MSM8512 - 70/85/10
ISSUE 4.3 : January 1999
Low V
cc
Data Retention Characteristics - L Version Only
(T
A
=-55°C to +125
o
C)
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retention
Operation Recovery Time
Symbol Test Condition
V
DR
I
CCDR
t
CDR
t
R
CS
≥
V
CC
-0.2V
V
CC
=3.0V, CS
≥
V
CC
-0.2V,
See Retention Waveform
See Retention Waveform
min
2.0
-
0
5
typ
-
-
-
-
max
5.5
250
-
-
Unit
V
µA
ns
ms
AC OPERATING CONDITIONS
Read Cycle
Parameter
Symbol
70
min max
70
-
-
-
10
10
5
0
0
-
70
70
35
-
-
-
25
25
85
min max
85
-
-
-
10
10
5
0
0
-
85
85
45
-
-
-
30
30
10
min max
100
-
-
-
10
10
5
0
0
-
100
100
50
-
-
-
30
30
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
t
RC
Address Access Time
t
AA
Chip Select Access Time
t
ACS
Output Enable to Output Valid
t
OE
Output Hold from Address Change
t
OH
Chip Selection to Output in Low Z
t
CLZ
Output Enable to Output in Low Z
t
OLZ
Chip Deselection to Output in High Z
(3)
t
CHZ
Output Disable to Output in High Z
(3)
t
OHZ
Write Cycle
Parameter
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
Output Disable to Output in High Z
Symbol
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
t
OHZ
70
min max
70
60
60
0
50
0
0
30
0
5
0
-
-
-
-
-
-
30
-
-
-
25
85
min max
85
75
75
0
55
5
0
35
0
5
0
-
-
-
-
-
-
30
-
-
-
30
10
min max
100
80
80
0
60
5
0
40
0
5
0
-
-
-
-
-
-
30
-
-
-
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
ISSUE 4.3 : January 1999
MSM8512 - 70/85/10
Read Cycle Timing Waveform
(1,2)
t
Address
RC
t
AA
OE
t
OE
t
OLZ
CS
t
OH
t
CLZ
t
ACS
t
CHZ(3)
t
OHZ(3)
D0~7
High-Z
Data Valid
Notes:
(1) During the Read Cycle, WE is high.
(2) Address valid prior to or coincident with CS transition Low.
(3) t
CHZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
to output voltage levels. These parameters are sampled and not 100% tested.
Write Cycle No.1 Timing Waveform
t
WC
Address
OE
t
AS(3)
t
AW
t
CW(4)
(6)
t
WR
(2)
CS
t
WP(1)
WE
t
OHZ(3,9)
D0~7 out
High-Z
t
DW
t
OW
t
DH
D0~7 in
High-Z
4
MSM8512 - 70/85/10
ISSUE 4.3 : January 1999
Write Cycle No.2 Timing Waveform
(5)
t
WC
Address
t
CW
CS
(6)
(4)
t
AW
t
WP(1)
WE
t
WR(2)
t
AS(3)
t
WHZ(3,9)
t
OW
High-Z
t
DW
t
OH
(8)
(7)
D0~7 out
t
DH
D0~7 in
High-Z
AC Characteristics Notes
(1) A write occurs during the overlap (t
WP
) of a low CS and a low WE.
(2) t
WR
is measured from the earlier of CS or WE going high to the end of write cycle.
(3) During this period, I/O pins are in the output state. Input signals out of phase must not be applied.
(4) If the CS low transition occurs simultaneously with the WE low transition or after the WE low transition, outputs remain
in a high impedance state.
(5) OE is continuously low. (OE=V
IL
)
(6) D
OUT
is in the same phase as written data of this write cycle.
(7) D
OUT
is the read data of next address.
(8) If CS is low during this period, I/O pins are in the output state. Input signals out of phase must not be applied.
(9) t
WHZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to
output voltage levels. These parameters are sampled and not 100% tested.
Low V
CC
Data Retention Timing Waveform
Vcc
DATA RETENTION MODE
4.5V
4.5V
t
CDR
2.2V
t
R
2.2V
V
DR
CS
0V
CS>Vcc-0.2V
5
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