MC74VHC1GT04
Inverting Buffer /
CMOS Logic Level Shifter
with LSTTL–Compatible Inputs
The MC74VHC1GT04 is a single gate inverting buffer fabricated
with silicon gate CMOS technology. It achieves high speed operation
similar to equivalent Bipolar Schottky TTL while maintaining CMOS
low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device input is compatible with TTL–type input thresholds and
the output has a full 5V CMOS level output swing. The input
protection circuitry on this device allows overvoltage tolerance on the
input, allowing the device to be used as a logic–level translator from
3.0V CMOS logic to 5.0V CMOS Logic or from 1.8V CMOS logic to
3.0V CMOS Logic while operating at the high–voltage power supply.
The MC74VHC1GT04 input structure provides protection when
voltages up to 7V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT04 to be used to interface 5V circuits to 3V
circuits. The output structures also provide protection when VCC = 0V.
These input and output structures help prevent device destruction
caused by supply voltage – input/output voltage mismatch, battery
backup, hot insertion, etc.
•
High Speed: tPD = 3.8ns (Typ) at VCC = 5V
•
Low Power Dissipation: ICC = 2µA (Max) at TA = 25°C
•
TTL–Compatible Inputs: VIL = 0.8V; VIH = 2.0V
•
CMOS–Compatible Outputs: VOH > 0.8VCC; VOL < 0.1VCC @Load
•
Power Down Protection Provided on Inputs and Outputs
•
Balanced Propagation Delays
•
Pin and Function Compatible with Other Standard Logic Families
•
Latchup Performance Exceeds 300mA
•
ESD Performance: HBM > 1500V; MM > 200V
http://onsemi.com
MARKING
DIAGRAMS
SC–88A / SOT–353/SC–70
DF SUFFIX
CASE 419A
VKd
Pin 1
d = Date Code
TSOP–5/SOT–23/SC–59
DT SUFFIX
CASE 483A
VKd
Pin 1
d = Date Code
PIN ASSIGNMENT
1
2
3
4
5
NC
IN A
GND
OUT Y
VCC
NC 1
IN A 2
GND 3
5 VCC
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
4 OUT Y
Figure 1. 5–Lead SOT–353 Pinout
(Top View)
LOGIC SYMBOL
IN A
1
OUT Y
FUNCTION TABLE
A Input
L
H
Y Output
H
L
©
Semiconductor Components Industries, LLC, 2000
1
June, 2000 – Rev. 2
Publication Order Number:
MC74VHC1GT04/D
MC74VHC1GT04
MAXIMUM RATINGS*
Characteristics
DC Supply Voltage
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current, per Pin
DC Supply Current, VCC and GND
Power dissipation in still air, SC–88A †
Lead temperature, 1 mm from case for 10 s
Storage temperature
(VOUT < GND; VOUT > VCC)
VCC = 0
High or Low State
Symbol
VCC
VIN
VOUT
IIK
IOK
IOUT
ICC
PD
TL
Value
–0.5 to +7.0
–0.5 to +7.0
–0.5 to 7.0
–0.5 to VCC + 0.5
–20
+20
+25
+50
200
260
Unit
V
V
V
mA
mA
mA
mA
mW
°C
Tstg
–65 to +150
°C
* Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied. Functional
operation should be restricted to the Recommended Operating Conditions.
†Derating — SC–88A Package: –3 mW/
_
C from 65
_
to 125
_
C
RECOMMENDED OPERATING CONDITIONS
Characteristics
DC Supply Voltage
DC Input Voltage
DC Output Voltage
VCC = 0
High or Low State
Symbol
VCC
VIN
VOUT
TA
tr , tf
Min
4.5
0.0
0.0
0.0
–55
0
0
Max
5.5
5.5
5.5
VCC
+125
100
20
Unit
V
V
V
°C
ns/V
Operating Temperature Range
Input Rise and Fall Time
VCC = 3.3V
±
0.3V
VCC = 5.0V
±
0.5V
The
q
JA of the package is equal to 1/Derating. Higher junction temperatures may affect the expected lifetime of the device per the table and
figure below.
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
Junction
Temperature
°C
80
90
100
110
120
130
140
NORMALIZED FAILURE RATE
Time, Hours
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
Time, Years
117.8
47.9
20.4
9.4
4.2
2.0
1.0
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
TJ = 120
°
C
TJ = 110
°
C
TJ = 130
°
C
TJ = 100
°
C
TJ = 80
°
C
100
TIME, YEARS
TJ = 90
°
C
1
1
10
1000
Figure 2. Failure Rate vs. Time
Junction Temperature
http://onsemi.com
2
MC74VHC1GT04
DC ELECTRICAL CHARACTERISTICS
VCC
Symbol
VIH
Parameter
Minimum High–Level
Input Voltage
Maximum Low–Level
Input Voltage
Minimum High–Level
Output Voltage
VIN = VIH or VIL
VIN = VIH or VIL
IOH = –50µA
VIN = VIH or VIL
IOH = –4mA
IOH = –8mA
VIN = VIH or VIL
IOL = 50µA
VIN = VIH or VIL
IOL = 4mA
IOL = 8mA
VIN = 5.5V or GND
VIN = VCC or GND
Input: VIN = 3.4V
VOUT = 5.5V
Test Conditions
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
3.0
4.5
3.0
4.5
3.0
4.5
0 to
5.5
5.5
5.5
0.0
2.9
4.4
2.58
3.94
0.0
0.0
0.1
0.1
0.36
0.36
±0.1
2.0
1.35
0.5
3.0
4.5
Min
1.4
2.0
2.0
0.53
0.8
0.8
2.9
4.4
2.48
3.80
0.1
0.1
0.44
0.44
±1.0
20
1.50
5.0
TA = 25°C
Typ
Max
TA
≤
85°C
Min
1.4
2.0
2.0
0.53
0.8
0.8
2.9
4.4
2.34
3.66
0.1
0.1
0.52
0.52
±1.0
40
1.65
10
µA
µA
mA
µA
V
V
Max
TA
≤
125°C
Min
1.4
2.0
2.0
0.53
0.8
0.8
Max
Unit
V
VIL
V
VOH
V
V
VOL
Maximum Low–Level
Output Voltage
VIN = VIH or VIL
IIN
ICC
ICCT
IOPD
Maximum Input
Leakage Current
Maximum Quiescent
Supply Current
Quiescent Supply
Current
Output Leakage
Current
ÎÎ
Î
Î
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î Î Î Î Î Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎ Î Î Î Î Î Î Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î Î Î Î Î Î
Î Î Î Î Î Î Î Î
Î
Î
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î Î Î Î Î Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î Î Î Î Î Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î Î Î Î Î Î
ÎÎ Î Î Î Î Î Î Î
Î Î Î Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î Î Î Î Î Î
Î Î
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î Î Î Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS
(Cload = 50 pF, Input tr = tf = 3.0ns)
Symbol
Parameter
Test Conditions
Min
TA = 25°C
Typ
5.0
6.2
3.8
4.2
5
TA
≤
85°C
TA
≤
125°C
Max
Min
Max
Min
Max
Unit
ns
tPLH,
tPHL
Maximum
Propogation Delay,
Input A to Y
VCC = 3.0
±
0.3V
VCC = 5.0
±
0.5V
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
10.0
13.5
6.7
7.7
10
11.0
15.0
7.5
8.5
10
13.0
17.5
8.5
9.5
10
CIN
Maximum Input
Capacitance
pF
Typical @ 25°C, VCC = 5.0V
10
CPD
Power Dissipation Capacitance (Note 1.)
pF
1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR
)
= CPD
VCC
fin + ICC. CPD is used to determine the no–load dynamic
power consumption; PD = CPD
VCC2
fin + ICC
VCC.
http://onsemi.com
3
MC74VHC1GT04
TEST POINT
A
50%
GND
tPLH
Y
tPHL
VOH
50% VCC
VOL
*Includes all probe and jig capacitance
3.0V
OUTPUT
DEVICE
UNDER
TEST
CL*
Figure 3. Switching Waveforms
DEVICE ORDERING INFORMATION
Device Nomenclature
Device
Order Number
MC74VHC1GT04DFT1
MC74VHC1GT04DFT2
MC74VHC1GT04DFR2
MC74VHC1GT04DTT2
MC74VHC1GT04DTR2
Circuit
Indicator
MC
MC
MC
MC
MC
Temp
Range
Identifier
74
74
74
74
74
Device
Function
T04
T04
T04
T04
T04
Package
Suffix
DF
DF
DF
DT
DT
Tape &
Reel
Suffix
T1
T2
R2
T2
R2
Figure 4. Test Circuit
Technology
VHC1G
VHC1G
VHC1G
VHC1G
VHC1G
Package Type
(Name/SOT#/
Common Name)
SC–88A / SOT–353
/ SC–70
SC–88A / SOT–353
/ SC–70
SC–88A / SOT–353
/ SC–70
TSOPS / SOT–23
/ SC–59
TSOPS / SOT–23
/ SC–59
Tape and
Reel Size
178 mm (7”)
3000 Unit
178 mm (7”)
3000 Unit
330 mm (13”)
10000 Unit
178 mm (7”)
3000 Unit
330 mm (13”)
10000 Unit
http://onsemi.com
4
MC74VHC1GT04
10 PITCHES
CUMULATIVE
TOLERANCE ON
TAPE
±0.2
mm
(±0.008”)
E
A0
B1
K0
SEE
NOTE 2
SEE NOTE 2
K
t
TOP
COVER
TAPE
D
P2
P0
F
W
+
B0
P
+
+
D1
FOR COMPONENTS
2.0 mm
×
1.2 mm
AND LARGER
FOR MACHINE REFERENCE
ONLY
INCLUDING DRAFT AND RADII
CONCENTRIC AROUND B0
EMBOSSMENT
USER DIRECTION OF FEED
CENTER LINES
OF CAVITY
*TOP COVER
TAPE THICKNESS (t1)
0.10 mm
(0.004”) MAX.
R MIN.
TAPE AND COMPONENTS
SHALL PASS AROUND RADIUS “R”
WITHOUT DAMAGE
BENDING RADIUS
EMBOSSED
CARRIER
EMBOSSMENT
10°
MAXIMUM COMPONENT ROTATION
TYPICAL
COMPONENT CAVITY
CENTER LINE
100 mm
(3.937”)
1 mm MAX
TAPE
1 mm
(0.039”) MAX
250 mm
(9.843”)
TYPICAL
COMPONENT
CENTER LINE
CAMBER (TOP VIEW)
ALLOWABLE CAMBER TO BE 1 mm/100 mm NONACCUMULATIVE OVER 250
mm
Figure 5. Carrier Tape Specifications
EMBOSSED CARRIER DIMENSIONS
(See Notes 1 and 2)
Tape
Size
8 mm
B1
Max
4.35 mm
(0.171”)
D
1.5 +0.1/
–0.0 mm
(0.059
+0.004/
–0.0”)
D1
1.0 mm
Min
(0.039”)
E
1.75
±0.1
mm
(0.069
±0.004”)
F
3.5
±0.5
mm
(1.38
±0.002”)
K
2.4 mm
(0.094”)
P
4.0
±0.10
mm
(0.157
±0.004”)
P0
4.0
±0.1
mm
(0.156
±0.004”)
P2
2.0
±0.1
mm
(0.079
±0.002”)
R
25 mm
(0.98”)
T
0.3
±0.05
mm
(0.01
+0.0038/
–0.0002”)
W
8.0
±0.3
mm
(0.315
±0.012”)
1. Metric Dimensions Govern–English are in parentheses for reference only.
2. A0, B0, and K0 are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to
0.50 mm max. The component cannot rotate more than 10° within the determined cavity
http://onsemi.com
5
京公网安备 11010802033920号
EEWORLD
