v5.7
ProASIC
PLUS®
Flash Family FPGAs
Features and Benefits
High Capacity
Commercial and Industrial
•
•
•
•
•
•
•
•
•
•
•
•
75,000 to 1 Million System Gates
27 k to 198 kbits of Two-Port SRAM
66 to 712 User I/Os
300, 000 to 1 million System Gates
72 k to 198 kbits of Two Port SRAM
158 to 712 User I/Os
0.22 µm 4 LM Flash-Based CMOS Process
Live At Power-Up (LAPU) Level 0 Support
Single-Chip Solution
No Configuration Device Required
Retains Programmed Design during Power-Down/Up Cycles
Mil/Aero Devices Operate over Full Military Temperature
Range
3.3 V, 32-Bit PCI, up to 50 MHz (33 MHz over military
temperature)
Two Integrated PLLs
External System Performance up to 150 MHz
The Industry’s Most Effective Security Key (FlashLock
®
)
Low Impedance Flash Switches
Segmented Hierarchical Routing Structure
Small, Efficient, Configurable (Combinatorial or Sequential)
Logic Cells
APA075
75,000
3,072
27 k
12
2
2
4
24
158
Yes
Yes
100, 144
208
–
144
APA150
150,000
6,144
36k
16
2
2
4
32
242
Yes
Yes
100
208
456
144, 256
APA300
1
300,000
8,192
72 k
32
2
2
4
32
290
Yes
Yes
–
208
456
144, 256
208, 352
APA450
450,000
12,288
108 k
48
2
2
4
48
344
Yes
Yes
–
208
456
144, 256, 484
APA600
1
600,000
21,504
126 k
56
2
2
4
56
454
Yes
Yes
–
208
456
256, 484, 676
208, 352
624
APA750
750,000
32,768
144 k
64
2
2
4
64
562
Yes
Yes
–
208
456
676, 896
®
High Performance Routing Hierarchy
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Ultra-Fast Local and Long-Line Network
High-Speed Very Long-Line Network
High-Performance, Low Skew, Splittable Global Network
100% Routability and Utilization
Schmitt-Trigger Option on Every Input
2.5 V/3.3 V Support with Individually-Selectable Voltage and
Slew Rate
Bidirectional Global I/Os
Compliance with PCI Specification Revision 2.2
Boundary-Scan Test IEEE Std. 1149.1 (JTAG) Compliant
Pin Compatible Packages across the ProASIC
PLUS
Family
PLL with Flexible Phase, Multiply/Divide and Delay
Capabilities
Internal and/or External Dynamic PLL Configuration
Two LVPECL Differential Pairs for Clock or Data Inputs
Flexibility with Choice of Industry-Standard Front-End Tools
Efficient Design through Front-End Timing and Gate Optimization
In-System Programming (ISP) via JTAG Port
SmartGen Netlist Generation Ensures Optimal Usage of
Embedded Memory Blocks
24 SRAM and FIFO Configurations with Synchronous and
Asynchronous Operation up to 150 MHz (typical)
I/O
Military
Reprogrammable Flash Technology
Unique Clock Conditioning Circuitry
Standard FPGA and ASIC Design Flow
ISP Support
SRAMs and FIFOs
Performance
•
•
•
•
•
•
•
Secure Programming
Low Power
Table 1 •
ProASIC
PLUS
Product Profile
Device
Maximum System Gates
Tiles (Registers)
Embedded RAM Bits (k=1,024 bits)
Embedded RAM Blocks (256x9)
LVPECL
PLL
Global Networks
Maximum Clocks
Maximum User I/Os
JTAG ISP
PCI
Package (by pin count)
TQFP
PQFP
PBGA
FBGA
CQFP
2
CCGA/LGA
2
Notes:
APA1000
1
1,000,000
56,320
198 k
88
2
2
4
88
712
Yes
Yes
–
208
456
896, 1152
208, 352
624
1. Available as Commercial/Industrial and Military/MIL-STD-883B devices.
2. These packages are available only for Military/MIL-STD-883B devices.
S e pt em be r 2 0 08
© 2008 Actel Corporation
i
See the Actel website for the latest version of the datasheet.
ProASIC
PLUS
Flash Family FPGAs
Ordering Information
APA1000
_
F
FG
G
1152
I
Application (Ambient Temperature Range)
Blank = Commercial (0˚C to +70˚C)
I = Industrial (-40˚C to +85˚C)
PP = Pre-production
ES = Engineering Silicon (Room Temperature Only)
M = Military (-55˚C to 125˚C)
B = MIL-STD-883 Class B
Package Lead Count
Lead-free packaging
Blank = Standard Packaging
G = RoHS Compliant Packaging
Package Type
TQ = Thin Quad Flat Pack (0.5 mm pitch)
PQ = Plastic Quad Flat Pack (0.5 mm pitch)
FG = Fine Pitch Ball Grid Array (1.0 mm pitch)
BG = Plastic Ball Grid Array (1.27 mm pitch)
CQ = Ceramic Quad Flat Pack (1.05 mm pitch)
CG = Ceramic Column Grid Array (1.27 mm pitch)
LG = Land Grid Array (1.27 mm pitch)
Speed Grade
Blank = Standard Speed
F = 20% Slower than Standard
Part Number
APA075
APA150
APA300
APA450
APA600
APA750
APA1000
=
=
=
=
=
=
=
75,000 Equivalent System Gates
150,000 Equivalent System Gates
300,000 Equivalent System Gates
450,000 Equivalent System Gates
600,000 Equivalent System Gates
750,000 Equivalent System Gates
1,000,000 Equivalent System Gates
ii
v5.7
ProASIC
PLUS
Flash Family FPGAs
Device Resources
User I/Os
2
Commercial/Industrial
Military/MIL-STD-883B
CCGA/
LGA
TQFP
TQFP
PQFP
PBGA FBGA FBGA FBGA FBGA FBGA
FBGA
CQFP
CQFP
100-Pin 144-Pin 208-Pin 456-Pin 144-Pin 256-Pin 484-Pin 676-Pin 896-Pin 1152-Pin 208-Pin 352-Pin 624-Pin
Device
APA075
APA150
APA300
APA450
APA600
APA750
APA1000
66
66
107
158
158
158
4
158
158
4
158
158
4
242
290
4
344
356
4
356
356
4
100
100
100
4
100
186
3
186
3, 4
186
3
186
3, 4
344
3
370
3
454
454
562
5
642
4, 5
712
5
158
248
440
158
248
440
158
248
Notes:
1. Package Definitions: TQFP = Thin Quad Flat Pack, PQFP = Plastic Quad Flat Pack, PBGA = Plastic Ball Grid Array, FBGA = Fine Pitch Ball Grid
Array, CQFP = Ceramic Quad Flat Pack, CCGA = Ceramic Column Grid Array, LGA = Land Grid Array
2. Each pair of PECL I/Os is counted as one user I/O.
3. FG256 and FG484 are footprint-compatible packages.
4. Military Temperature Plastic Package Offering
5. FG896 and FG1152 are footprint-compatible packages.
General Guideline
Maximum performance numbers in this datasheet are based on characterized data. Actel does not guarantee
performance beyond the limits specified within the datasheet.
v5.7
iii
ProASIC
PLUS
Flash Family FPGAs
Temperature Grade Offerings
Package
TQ100
TQ144
PQ208
BG456
FG144
FG256
FG484
FG676
FG896
FG1152
CQ208
CQ352
CG624
Note:
C = Commercial
I = Industrial
M = Military
B = MIL-STD-883
M, B
M, B
M, B
M, B
M, B
C, I
APA075
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I, M
C, I, M
C, I, M
C, I, M
C, I
C, I
C, I
C, I
C, I
C, I, M
C, I, M
C, I, M
C, I
C, I
C, I, M
C, I
M, B
M, B
M, B
C, I, M
C, I, M
C, I
C, I
C, I, M
C, I, M
APA150
C, I
APA300
APA450
APA600
APA750
APA1000
Speed Grade and Temperature Matrix
–F
C
I
M, B
Note:
C = Commercial
I = Industrial
M = Military
B = MIL-STD-883
✓
Std.
✓
✓
✓
iv
v5.7
ProASIC
PLUS
Flash Family FPGAs
Table of Contents
General Description
ProASIC
PLUS
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Timing Control and Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
Sample Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
Adjustable Clock Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
Clock Skew Minimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
PLL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27
ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29
Calculating Typical Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-33
Tristate Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-42
Output Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Global Input Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Predicted Global Routing Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-44
1-46
1-48
1-50
Global Routing Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-50
Module Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-51
Sample Macrocell Library Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-51
Embedded Memory Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-54
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-73
Recommended Design Practice for V
PN
/V
PP
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-74
Package Pin Assignments
100-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
144-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
208-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
352-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
456-Pin PBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
144-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37
256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40
484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45
676-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51
896-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59
1152-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-69
624-Pin CCGA/LGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-78
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Data Sheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Export Administration Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
v5.7
v
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