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74ACT14MTC

Description
ACT SERIES, HEX 1-INPUT INVERT GATE, PDSO14
Categorylogic    logic   
File Size130KB,9 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Environmental Compliance
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74ACT14MTC Overview

ACT SERIES, HEX 1-INPUT INVERT GATE, PDSO14

74ACT14MTC Parametric

Parameter NameAttribute value
Brand NameFairchild Semiconduc
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerFairchild
Parts packaging codeTSSOP
package instructionTSSOP, TSSOP14,.25
Contacts14
Manufacturer packaging code14 LD,TSSOP,JEDEC MO-153, 4.4MM WIDE
Reach Compliance Codecompli
ECCN codeEAR99
seriesACT
JESD-30 codeR-PDSO-G14
JESD-609 codee4
length5 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeINVERTER
MaximumI(ol)0.024 A
Humidity sensitivity level1
Number of functions6
Number of entries1
Number of terminals14
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP14,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packingRAIL
Peak Reflow Temperature (Celsius)260
power supply5 V
Prop。Delay @ Nom-Su11 ns
propagation delay (tpd)11 ns
Certification statusNot Qualified
Schmitt triggerYES
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceNickel/Palladium/Gold (Ni/Pd/Au)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width4.4 mm
Base Number Matches1
74AC14 • 74ACT14 Hex Inverter with Schmitt Trigger Input
November 1988
Revised September 2005
74AC14 • 74ACT14
Hex Inverter with Schmitt Trigger Input
General Description
The 74AC14 and 74ACT14 contain six inverter gates each with
a Schmitt trigger input. They are capable of transforming slowly
changing input signals into sharply defined, jitter-free output sig-
nals. In addition, they have a greater noise margin than conven-
tional inverters.
The 74AC14 and 74ACT14 have hysteresis between the posi-
tive-going and negative-going input thresholds (typically 1.0V)
which is determined internally by transistor ratios and is essen-
tially insensitive to temperature and supply voltage variations.
Features
O
I
CC
reduced by 50%
O
Outputs source/sink 24 mA
O
74ACT14 has TTL-compatible inputs
Ordering Code:
Order Number
74AC14SC
74AC14SCX_NL
(Note 1)
74AC14SJ
74AC14MTC
74AC14MTCX_NL
(Note 1)
74AC14PC
74ACT14SC
74ACT14MTC
74ACT14MTCX_NL
(Note 1)
74ACT14PC
Package
Number
M14A
M14A
M14D
MTC14
MTC14
N14A
M14A
MTC14
MTC14
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1:
“_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
FACT
¥
is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS009917
www.fairchildsemi.com
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