STK15C88
256-Kbit (32 K × 8) PowerStore nvSRAM
256-Kbit (32 K × 8) PowerStore nvSRAM
Features
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Functional Description
The Cypress STK15C88 is a 256Kb fast static RAM with a
nonvolatile element in each memory cell. The embedded
nonvolatile elements incorporate QuantumTrap
™
technology
producing the world’s most reliable nonvolatile memory. The
SRAM provides unlimited read and write cycles, while
independent, nonvolatile data resides in the highly reliable
QuantumTrap cell. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile memory.
Both the STORE and RECALL operations are also available
under software control.
PowerStore nvSRAM products depend on the intrinsic system
capacitance to maintain system power long enough for an
automatic store on power loss. If the power ramp from 5 volts to
3.6 volts is faster than 10 ms, consider our 14C88 or 16C88 for
more reliable operation.
25 ns and 45 ns Access Times
Pin compatible with Industry Standard SRAMs
Automatic Nonvolatile STORE on power loss
Nonvolatile STORE under Software Control
Automatic RECALL to SRAM on Power Up
Unlimited Read/Write Endurance
Unlimited RECALL Cycles
1,000,000 STORE Cycles
100 year Data Retention
Single 5 V + 10% Power Supply
Commercial and Industrial Temperatures
28-pin (300 mil and 330 mil) SOIC packages
RoHS Compliance
Logic Block Diagram
Cypress Semiconductor Corporation
Document Number: 001-50593 Rev. *C
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198 Champion Court
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San Jose
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CA 95134-1709
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408-943-2600
Revised April 10, 2011
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STK15C88
Contents
Pin Configurations ........................................................... 3
Device Operation .............................................................. 4
SRAM Read ....................................................................... 4
SRAM Write ....................................................................... 4
AutoStore Operation ........................................................ 4
Hardware RECALL (Power Up) ........................................ 4
Software STORE ............................................................... 4
Software RECALL ............................................................. 4
Hardware Protect .............................................................. 5
Noise Considerations ....................................................... 5
Low Average Active Power .............................................. 5
Best Practices ................................................................... 5
Maximum Ratings ............................................................. 7
DC Electrical Characteristics .......................................... 7
Data Retention and Endurance ....................................... 8
Capacitance ...................................................................... 8
Thermal Resistance .......................................................... 8
AC Test Conditions .......................................................... 8
AC Switching Characteristics ......................................... 9
SRAM Read Cycle ............................................................. 9
Switching Waveforms ...................................................... 9
SRAM Write Cycle .......................................................... 10
Switching Waveforms .................................................... 10
AutoStore or Power Up RECALL .................................. 11
Switching Waveforms .................................................... 11
Software Controlled STORE/RECALL Cycle ................ 12
Ordering Information ...................................................... 13
Ordering Code Definitons .......................................... 13
Package Diagrams .......................................................... 14
Document History Page ................................................. 16
Sales, Solutions and Legal Information ....................... 17
Worldwide Sales and Design Support ....................... 17
Products .................................................................... 17
PSoC Solutions ......................................................... 17
Document Number: 001-50593 Rev. *C
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STK15C88
Pin Configurations
Figure 1. Pin Diagram - 28-pin SOIC
Table 1. Pin Definitions - 28-pin SOIC
Pin Name
A
0
–A
14
DQ
0
-DQ
7
WE
CE
OE
V
SS
V
CC
Alt
I/O Type
Input
Input or
Output
Input
Input
Input
Document Number: 001-50593 Rev. *C
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Description
Address Inputs.
Used to select one of the 32,768 bytes of the nvSRAM.
Bidirectional Data I/O lines.
Used as input or output lines depending on operation.
Write Enable Input, Active LOW.
When the chip is enabled and WE is LOW, data on the
I/O pins is written to the specific address location.
Chip Enable Input, Active LOW.
When LOW, selects the chip. When HIGH, deselects the
chip.
W
E
G
Output Enable, Active LOW.
The active LOW OE input enables the data output buffers
during read cycles. Deasserting OE HIGH causes the I/O pins to tristate.
Ground for the Device.
The device is connected to ground of the system.
N
Ground
Power Supply
Power Supply Inputs to the Device.
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STK15C88
Device Operation
The STK15C88 is a versatile memory chip that provides several
modes of operation. The STK15C88 can operate as a standard
32 K × 8 SRAM. It has a 32 K × 8 nonvolatile element shadow to
which the SRAM information can be copied, or from which the
SRAM can be updated in nonvolatile mode.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The STK15C88 software STORE
cycle is initiated by executing sequential CE controlled READ
cycles from six specific address locations in exact order. During
the STORE cycle, an erase of the previous nonvolatile data is
first performed, followed by a program of the nonvolatile
elements. When a STORE cycle is initiated, input and output are
disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other READ or WRITE
accesses intervene in the sequence. If they intervene, the
sequence is aborted and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following READ
sequence is performed:
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0FC0, Initiate STORE cycle
SRAM Read
The STK15C88 performs a READ cycle whenever CE and OE
are LOW while WE is HIGH. The address specified on pins A
0–14
determines the 32,768 data bytes accessed. When the READ is
initiated by an address transition, the outputs are valid after a
delay of t
AA
(READ cycle 1). If the READ is initiated by CE or OE,
the outputs are valid at t
ACE
or at t
DOE
, whichever is later (READ
cycle 2). The data outputs repeatedly respond to address
changes within the t
AA
access time without the need for transi-
tions on any control input pins, and remains valid until another
address change or until CE or OE is brought HIGH.
A WRITE cycle is performed whenever CE and WE are LOW.
The address inputs must be stable prior to entering the WRITE
cycle and must remain stable until either CE or WE goes HIGH
at the end of the cycle. The data on the common I/O pins DQ
0–7
are written into the memory if it has valid t
SD
, before the end of
a WE controlled WRITE or before the end of an CE controlled
WRITE. Keep OE HIGH during the entire WRITE cycle to avoid
data bus contention on common I/O lines. If OE is left LOW,
internal circuitry turns off the output buffers t
HZWE
after WE goes
LOW.
AutoStore Operation
The STK15C88 uses the intrinsic system capacitance to perform
an automatic STORE on power down. As long as the system
power supply takes at least t
STORE
to decay from V
SWITCH
down
to 3.6 V, the STK15C88 will safely and automatically store the
SRAM data in nonvolatile elements on power down.
In order to prevent unneeded STORE operations, automatic
STOREs will be ignored unless at least one WRITE operation
has taken place since the most recent STORE or RECALL cycle.
Software initiated STORE cycles are performed regardless of
whether a WRITE operation has taken place.
Hardware RECALL (Power Up)
During power up or after any low power condition (V
CC
<
V
RESET
), an internal RECALL request is latched. When V
CC
once again exceeds the sense voltage of V
SWITCH
, a RECALL
cycle is automatically initiated and takes t
HRECALL
to complete.
If the STK15C88 is in a WRITE state at the end of power up
RECALL, the SRAM data is corrupted. To help avoid this
situation, a 10 Kohm resistor is connected either between WE
and system V
CC
or between CE and system V
CC
.
Document Number: 001-50593 Rev. *C
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The software sequence is clocked with CE controlled READs.
When the sixth address in the sequence is entered, the STORE
cycle commences and the chip is disabled. It is important that
READ cycles and not WRITE cycles are used in the sequence.
It is not necessary that OE is LOW for a valid sequence. After the
t
STORE
cycle time is fulfilled, the SRAM is again activated for
READ and WRITE operation.
Software RECALL
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Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of READ operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled READ operations is
performed:
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0C63, Initiate RECALL cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared, and then the nonvolatile information is transferred into
the SRAM cells. After the t
RECALL
cycle time, the SRAM is once
again ready for READ and WRITE operations. The RECALL
operation does not alter the data in the nonvolatile elements. The
nonvolatile data can be recalled an unlimited number of times.
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STK15C88
Hardware Protect
The STK15C88 offers hardware protection against inadvertent
STORE operation and SRAM WRITEs during low voltage
conditions. When V
CAP
<V
SWITCH
, all externally initiated STORE
operations and SRAM WRITEs are inhibited.
Figure 3. Current Versus Cycle Time (READ)
Noise Considerations
The STK15C88 is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between V
CC
and V
SS,
using leads and traces that are as short
as possible. As with all high speed CMOS ICs, careful routing of
power, ground, and signals reduce circuit noise.
Figure 2. Current Versus Cycle Time (WRITE)
Document Number: 001-50593 Rev. *C
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CMOS technology provides the STK15C88 the benefit of
drawing significantly less current when it is cycled at times longer
than 50 ns.
Figure 2
and
Figure 3
show the relationship between
I
CC
and READ or WRITE cycle time. Worst case current
consumption is shown for both CMOS and TTL input levels
(commercial temperature range, V
CC
= 5.5 V, 100% duty cycle
on chip enable). Only standby current is drawn when the chip is
disabled. The overall average current drawn by the STK15C88
depends on the following items:
1. The duty cycle of chip enable
2. The overall cycle rate for accesses
3. The ratio of READs to WRITEs
4. CMOS versus TTL input levels
5. The operating temperature
6. The V
CC
level
7. I/O loading
Best Practices
nvSRAM products have been used effectively for over 15 years.
While ease-of-use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
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The nonvolatile cells in an nvSRAM are programmed on the
test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites, sometimes, reprogram these values. Final NV patterns
are typically repeating patterns of AA, 55, 00, FF, A5, or 5A.
End product’s firmware should not assume a NV array is in a
set programmed state. Routines that check memory content
values to determine first time system configuration and cold or
warm boot status should always program a unique NV pattern
(for example, complex 4-byte pattern of 46 E6 49 53 hex or
more random bytes) as part of the final system manufacturing
test to ensure these system routines work consistently.
Power up boot firmware routines should rewrite the nvSRAM
into the desired state. While the nvSRAM is shipped in a preset
state, best practice is to again rewrite the nvSRAM into the
desired state as a safeguard against events that might flip the
bit inadvertently (program bugs and incoming inspection
routines).
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