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5962H9658301QXA

Description
Parity Generator/Checker, ACT Series, 9-Bit, Complementary Output, CMOS, CDFP14, BOTTOM BRAZED, CERAMIC, DFP-14
Categorylogic    logic   
File Size205KB,16 Pages
ManufacturerCobham PLC
Download Datasheet Parametric View All

5962H9658301QXA Overview

Parity Generator/Checker, ACT Series, 9-Bit, Complementary Output, CMOS, CDFP14, BOTTOM BRAZED, CERAMIC, DFP-14

5962H9658301QXA Parametric

Parameter NameAttribute value
MakerCobham PLC
package instructionBOTTOM BRAZED, CERAMIC, DFP-14
Reach Compliance Codeunknown
ECCN code3A001.A.1.A
Other featuresODD/EVEN PARITY GENERATOR
seriesACT
JESD-30 codeR-XDFP-F14
JESD-609 codee0
length9.525 mm
Logic integrated circuit typePARITY GENERATOR/CHECKER
Number of digits9
Number of functions1
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output polarityCOMPLEMENTARY
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDFP
Encapsulate equivalent codeFL14,.3
Package shapeRECTANGULAR
Package formFLATPACK
power supply5 V
propagation delay (tpd)20 ns
Certification statusQualified
Filter level38535Q/M;38534H;883B
Maximum seat height2.921 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTIN LEAD
Terminal formFLAT
Terminal pitch1.27 mm
Terminal locationDUAL
total dose1M Rad(Si) V
width6.2865 mm
Base Number Matches1
REVISIONS
LTR
A
B
DESCRIPTION
Changes in accordance with NOR 5962-R097-97. – CFS
Add limit for linear energy threshold (LET) with no latch-up in section 1.5.
Update the boilerplate to the requirements of MIL-PRF-38535. Editorial
changes throughout. – TVN
Update boilerplate paragraphs and radiation paragraphs 4.4.4.1 – 4.4.4.4 to
the current MIL-PRF-38535 requirements. - LTG
To correct switching waveforms input/output test limits to figure 4. Add test
equivalent circuits and footnote 5 to figure 4. Add paragraph 2.2 for ASTM
F1192 document. Delete class M requirements throughout.—MAA
DATE (YR-MO-DA)
96-11-18
06-03-20
APPROVED
Monica L. Poelking
Thomas M. Hess
C
12-04-19
Thomas M. Hess
D
13-02-05
Thomas M. Hess
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
PMIC N/A
D
15
REV
SHEET
PREPARED BY
Thanh V. Nguyen
CHECKED BY
Thanh V. Nguyen
APPROVED BY
Monica L. Poelking
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
DSCC FORM 2233
APR 97
DRAWING APPROVAL DATE
96-05-20
REVISION LEVEL
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D
10
D
11
D
12
D
13
D
14
STANDARD
MICROCIRCUIT
DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil
MICROCIRCUIT, DIGITAL, RADIATION
HARDENED, ADVANCED CMOS, 9-BIT
ODD/EVEN PARITY GENERATOR/CHECKER, TTL
COMPATIBLE INPUTS
,
MONOLITHIC SILICON
SIZE
CAGE CODE
D
A
67268
SHEET
1 OF 15
5962-96583
5962-E276-12

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