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HC6856YVFCC40

Description
32K x 8 STATIC RAM
File Size158KB,12 Pages
ManufacturerHoneywell
Websitehttp://www.ssec.honeywell.com/
Download Datasheet View All

HC6856YVFCC40 Overview

32K x 8 STATIC RAM

Military & Space Products
32K x 8 STATIC RAM
FEATURES
RADIATION
• Fabricated with RICMOS
IV Bulk
0.8
µm
Process (L
eff
= 0.65
µm)
• Total Dose Hardness through 1x10
6
rad(SiO
2
)
• Neutron Hardness through 1x10
14
cm
-2
• Dynamic and Static Transient Upset Hardness
through 1x10
9
rad(Si)/s
• Soft Error Rate of <1x10
-10
upsets/bit-day
• Dose Rate Survivability through 1x10
12
rad(Si)/s
• Latchup Free
OTHER
HC6856
• Listed on SMD #5962-92153. Available as
MIL-PRF-38535 QML Class Q and Class V
• Read/Write Cycle Times
30 ns (Typical)
40 ns (-55 to 125°C)
• Standby Current of 20
µA
(typical)
• Asynchronous Operation
• CMOS or TTL Compatible I/O
• Single 5 V
±
10% Power Supply
• Packaging Options
- 36-Lead Flat Pack (0.630 in. x 0.650 in.)
- 28-Lead Flat Pack (0.530 in. x 0.720 in.)
- 28-Lead DIP, MIL-STD-1835, CDIP2-T28
GENERAL DESCRIPTION
The 32K x 8 Radiation Hardened Static RAM is a high
performance 32,768 x 8-bit static random access memory
with industry-standard functionality. It is fabricated with
Honeywell’s radiation hardened technology, and is de-
signed for use in systems operating in radiation environ-
ments. The RAM operates over the full military temperature
range and requires only a single 5 V
±
10% power supply.
The RAM is available with either TTL or CMOS compatible
I/O. Power consumption is typically less than 50 mW/MHz
in operation, and less than 5 mW/MHz in the low power
disabled mode. The RAM read operation is fully asynchro-
nous, with an associated typical access time of 20 ns.
Honeywell’s enhanced RICMOS
IV (Radiation Insensitive
CMOS) technology is radiation hardened through the use of
advanced and proprietary design, layout, and process hard-
ening techniques. The RICMOS
IV process is a 5-volt,
twin-well CMOS technology with a 170 Å gate oxide and a
minimum drawn feature size of 0.8
µm
(0.65
µm
effective
gate length—L
eff
). Additional features include a three layer
interconnect metalization and a lightly doped drain (LDD)
structure for improved short channel reliability. High resis-
tivity cross-coupled polysilicon resistors have been incorpo-
rated for single event upset hardening.
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