IDT70V7519S_09 datasheet, PDF - EEWORLD Datasheet

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IDT70V7519S_09: Description256K X 36 DUAL-PORT SRAM, 15 ns, PBGA256; Categorystorage; File Size242KB，22 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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IDT70V7519S_09 Overview

256K X 36 DUAL-PORT SRAM, 15 ns, PBGA256

IDT70V7519S_09 Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	256
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	3.45 V
Minimum supply/operating voltage	3.15 V
Rated supply voltage	3.3 V
maximum access time	15 ns
Processing package description	BGA-256
state	ACTIVE
packaging shape	SQUARE
Package Size	GRID array, low PROFILE
surface mount	Yes
Terminal form	BALL
Terminal spacing	1 mm
terminal coating	tin lead
Terminal location	BOTTOM
Packaging Materials	Plastic/Epoxy
Temperature level	INDUSTRIAL
memory width	36
organize	256K × 36
storage density	9.44E6 deg
operating mode	Synchronize
Number of digits	262144 words
Number of digits	256K
Memory IC type	dual-port static random access memory
serial parallel	parallel

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HIGH-SPEED 3.3V 256K x 36

SYNCHRONOUS

IDT70V7519S

BANK-SWITCHABLE

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

Features:

◆

256K x 36 Synchronous Bank-Switchable Dual-ported

SRAM Architecture

–

64 independent 4K x 36 banks

– 9 megabits of memory on chip

Bank access controlled via bank address pins

High-speed data access

– Commercial: 3.4ns(200MHz)/3.6ns (166MHz)/4.2ns

(133MHz) (max.)

– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)

Selectable Pipelined or Flow-Through output mode

Counter enable and repeat features

Dual chip enables allow for depth expansion without

additional logic

Full synchronous operation on both ports

– 5ns cycle time, 200MHz operation (14Gbps bandwidth)

– Fast 3.4ns clock to data out

◆

– 1.5ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 200MHz

– Data input, address, byte enable and control registers

– Self-timed write allows fast cycle time

Separate byte controls for multiplexed bus and bus

matching compatibility

LVTTL- compatible, 3.3V (±150mV) power supply

for core

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V (±100mV)

power supply for I/Os and control signals on each port

Industrial temperature range (-40°C to +85°C) is

available at 166MHz and 133MHz

Available in a 208-pin Plastic Quad Flatpack (PQFP),

208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball

Grid Array (BGA)

Supports JTAG features compliant with IEEE 1149.1

Green parts available, see ordering information

Functional Block Diagram

PL/FT

OPT

CLK

ADS

CNTEN

REPEAT

R/W

PL/FT

OPT

CLK

ADS

CNTEN

REPEAT

R/W

CONTROL

LOGIC

MUX

4Kx36

MEMORY

ARRAY

(BANK 0)

MUX

CONTROL

LOGIC

I/O

0L-35L

I/O

CONTROL

MUX

4Kx36

MEMORY

ARRAY

(BANK 1)

MUX

I/O

CONTROL

I/O

0R-35R

11L

ADDRESS

DECODE

ADDRESS

DECODE

11R

BANK

DECODE

MUX

4Kx36

MEMORY

ARRAY

(BANK 63)

BANK

DECODE

NOTE:

1. The Bank-Switchable dual-port uses a true SRAM

core instead of the traditional dual-port SRAM core.

As a result, it has unique operating characteristics.

Please refer to the functional description on page 19

for details.

MUX

TDI

TDO

JTAG

TMS

TCK

TRST

5618 drw 01

JUNE 2015

DSC 5618/9

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