JCB0305D24 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > semiconductor> Analog mixed-signal IC> JCB0305D24

JCB0305D24: DescriptionXP POWER - JCB0305S05 - DC-DC CONV; ISO POL; 1 O/P; 3W; 600mA; 5V; Categorysemiconductor Analog mixed-signal IC; File Size246KB，2 Pages; ManufacturerXP Power; Websitehttps://www.xppower.com/

Download Datasheet View All

JCB0305D24 Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	JCB0305D24	-	-	View	Buy Now

JCB0305D24 Overview

XP POWER - JCB0305S05 - DC-DC CONV; ISO POL; 1 O/P; 3W; 600mA; 5V

Preview

Download Datasheet

View All

DC DC

3 Watts

JCB Series

•

2:1 Input Range

xppower.com

Operating Temperature 40 °C to +100 °C

Single & Dual Outputs

1500 VDC Isolation

Optional Isolation to 3000 VDC

Optional Metal Case

3 Year Warranty

Specification

Input

• 5 V (4.5-9 VDC)

12 V (9-18 VDC)

24 V (18-36 VDC)

48 V (36-72 VDC)

Input Current

• See table

Input Filter

• Pi network

Input Reflected Ripple

• 35 mA pk-pk through 12 µH inductor

Input Surge

• 5 V models 15 VDC for 100 ms

12 V models 24 VDC for 100 ms

24 V models 40 VDC for 100 ms

48 V models 80 VDC for 100 ms

Undervoltage Lockout

• None

Reverse Voltage

• None

Protection

Input Voltage Range

General

Efficiency

Isolation Voltage

• See tables

• 1500 VDC Input to Output

For optional high isolation version 3000 VDC

(see note 3)

1500 VDC Input to Case

1500 VDC Output to Case

• 100-400 kHz variable

Switching Frequency

Isolation Resistance

Power Density

MTBF

• 10

Ω

• 7.5 W/in

• >2 MHrs to MIL-HDBK-217F at 25 °C, GB

Environmental

Operating Temperature

• -40 °C to +100 °C, derate from 100% load

at +85 °C to no load at +100 °C

Case Temperature

• +100 °C max

Storage Temperature

• -40 °C to +125 °C

Humidity

• Up to 95% RH, non-condensing

Cooling

• Natural convection

Output

Output Voltage

Minimum Load

Initial Set Accuracy

Line Regulation

Load Regulation

Cross Regulation

Transient Response

Ripple & Noise

Short Circuit Protection

Overvoltage Protection

Overcurrent Protection

Maximum Capacitive

Load

Temperature

Coefficient

•

See table

Minimum load required (see note 1)

±1% max

±0.5% max

±5% on dual output models (see note 2)

<3% deviation, recovery to within 1% in

2 ms for a 50% load change

60 mV pk-pk max, 20 MHz bandwidth

Continuous, with auto recovery

None

See tables

EMC & Safety

Emissions

• EN55022 Class A conducted &

radiated, with external components,

see application note

• EN61000-4-2, level 3, Perf Criteria A

• EN61000-4-4, level 3, Perf Criteria A

(see note 7)

• EN61000-4-5, installation class 3,

Perf Criteria A (see note 7)

• EN61000-4-6, 10 V rms, Perf Criteria A

• EN61000-4-8, 1 A/m, Perf Criteria A

ESD Immunity

EFT/Burst

Surge

Conducted Immunity

Magnetic Fields

• ±0.02/°C max

Recommended Resources

Digital isolator Si8641 typical circuit and OBC controller system

Pressure signal conditioning circuit circuit diagram based on MAX1450

Five-segment spectrum display circuit

Simple window detector circuit diagram

Oil concentration meter sampling and holding circuit

Welding machine no-load power-saving circuit

Please tell me the output voltage of the bidirectional thyristor circuit: Excuse me, what determines the voltage range on the right side of this graph? How can I see the lowest and highest V?...; sky999 PCB Design

I encountered many problems in my study as shown in the figure (I am a hardware developer and just learned C): #include stdio.h/* count digits, white space, others */main(){int c, i, nwhite, nother;int ndigit[10];nwhite = nother = 0;for (i = 0; i10; ++i)ndigit[i] = 0;while ((c = getchar()) != EOF)if (c = '0'c ...; QWE4562009 MCU

How to consider and design ESD of RF modules?: When hardware engineers design products, ESD immunity is an important consideration. Static electricity is harmful to most electronic products, and RF modules are more sensitive to static electricity....; 火辣西米秀 Wireless Connectivity

Verilog module content: The port of the module declares the input and output ports of the module. Its format is as follows:module module name (port 1, port 2, port 3, port 4, ………);module content:the content of the module inc...; 至芯科技FPGA大牛 FPGA/CPLD

Share interactive Q&A with TI experts | Design and optimization of buck-boost charging chip compatible with USB-PD protocol: [i=s]This post was last edited by qwqwqw2088 on 2020-8-17 11:36[/i]...; qwqwqw2088 Analogue and Mixed Signal

KiCad open source component library collection: KiCad officialhttps://gitee.com/KiCAD-CNhttps://github.com/kicad Digikey KiCad component libraryhttps://github.com/digikey/digikey-kicad-library KiCad component library of Jiali Chuang/LiChuang Mallht...; qwqwqw2088 PCB Design

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components