24C02 / 24C04 / 24C08 / 24C16
Features
¡
Wide Voltage Operation
- V
CC
= 1.8V to 5.5V
¡
Operating Ambient Temperature: -40
。
to +85
。
C
C
¡
Internally Organized:
- 24C02, 256 X 8 (2K bits)
- 24C04, 512 X 8 (4K bits)
- 24C08, 1024 X 8 (8K bits)
- 24C16, 2048 X 8 (16K bits)
¡
1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility
¡
Write Protect Pin for Hardware Data Protection
¡
8-byte Page (2K), 16-byte Page (4K, 8K, 16K) Write Modes
¡
Partial Page Writes Allowed
¡
Self-timed Write Cycle (5 ms max)
¡
High-reliability
- Endurance: 1 Million Write Cycles
- Data Retention: 100 Years
¡
Two-wire Serial Interface
¡
Schmitt Trigger, Filtered Inputs for Noise Suppression
¡
Bidirectional Data Transfer Protocol
General Description
The
¡
8-lead PDIP, 8-lead SOP and 8-lead TSSOP Packages
¡
Die Sales: Wafer Form, Waffle Pack
24C02/ 24C04/ 24C08/ 24C16 provides 2048/4096/8192/16384 bits of serial electrically erasable and
programmable read-only memory (EEPROM) organized as 256/512/1024/2048 words of 8 bits each. The device is
optimized for use in many industrial and commercial applications where low-power and low-voltage operation are
essential. The
24C02/ 24C04/ 24C08/ 24C16 is available in space-saving 8-lead PDIP, 8-lead SOP, and 8-lead
TSSOP packages and is accessed via a two-wire serial interface.
Pin Configuration
8-lead PDIP
C16 / C08 / C04 / C02
NC / NC / NC / A0
NC / NC / A1 / A1
NC / A2 / A2 / A2
GND
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
C16 / C08 / C04 / C02
NC / NC / NC / A0
NC / NC / A1 / A1
NC / A2 / A2 / A2
GND
8-lead SOP
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
8-lead TSSOP
C16 / C08 / C04 / C02
NC / NC / NC / A0
NC / NC / A1 / A1
NC / A2 / A2 / A2
GND
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
Pin Descriptions
¡
Table 1: Pin Configuration
Pin Designation
Type
Name and Functions
A0 - A2
SDA
SCL
WP
GND
V
CC
NC
I
Address Inputs
Serial Data
Serial Clock Input
Write Protect
Ground
Power Supply
No Connect
I/O & Open-drain
I
I
P
P
NC
BEIJING ESTEK ELECTRONICS CO.,LTD
1
24C02 / 24C04 / 24C08 / 24C16
Block Diagram
V
CC
GND
WP
SCL
SDA
START STOP
LOGIC
EN
SERIAL CONTROL
LOGIC
LOAD
COMP
DEVICE ADDRESS
COMPARATOR
HIGH VOLTAGE
PUMP/TIMING
DATA RECOVERY
C16 / C08 / C04 / C02
NC / NC / NC / A0
NC / NC / A1 / A1
NC / A2 / A2 / A2
DATA WORD
ADDRESS COUNTER
LOAD
INC
X DECODER
EEPROM
Y DECODER
SERIAL MUX
DIN
DOUT/ACKNOWLEDGE
DOUT
BEIJING ESTEK ELECTRONICS CO.,LTD
2
24C02 / 24C04 / 24C08 / 24C16
Pin Descriptions
DEVICE/PAGE ADDRESSES (A2, A1 and A0):
The A2, A1 and A0 pins are device address inputs that are hard
wired for the
The
The
The
24C02. Eight 2K devices may be addressed on a single bus system (device addressing is discussed in
detail under the Device Addressing section).
24C04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K devices may be addressed on a
24C08 only uses the A2 input for hardwire addressing and a total of two 8K devices may be addressed on a single
24C16 does not use the device address pins, which limits the number of devices on a single bus to one. The A0,
single bus system. The A0 pin is a no connect and can be connected to ground.
bus system. The A0 and A1 pins are no connects and can be connected to ground.
A1 and A2 pins are no connects and can be connected to ground.
SERIAL DATA (SDA):
The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be
wire-ORed with any number of other open-drain or open- collector devices.
SERIAL CLOCK (SCL):
The SCL input is used to positive edge clock data into each EEPROM device and negative
edge clock data out of each device.
WRITE PROTECT (WP):
The
24C02/ 24C04/ 24C08/ 24C16 has a Write Protect pin that provides hardware data
protection. The Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write
Protect pin is connected to V
CC
, the write protection feature is enabled and operates as shown in the following Table 2.
¡
Table 2: Write Protect
WP Pin Status
Part of the Array Protected
24C02
Full (2K) Array
24C04
Full (4K) Array
24C08
Full (8K) Array
24C16
Full (16K) Array
At V
CC
At GND
Normal Read / Write Operations
Memory Organization
24C02, 2K SERIAL EEPROM:
Internally organized with 32 pages of 8 bytes each, the 2K requires an 8-bit data
word address for random word addressing.
24C04, 4K SERIAL EEPROM:
Internally organized with 32 pages of 16 bytes each, the 4K requires a 9-bit data
word address for random word addressing.
24C08, 8K SERIAL EEPROM:
Internally organized with 64 pages of 16 bytes each, the 8K requires a 10-bit data
word address for random word addressing.
24C16, 16K SERIAL EEPROM:
Internally organized with 128 pages of 16 bytes each, the 16K requires an 11-bit
data word address for random word addressing.
BEIJING ESTEK ELECTRONICS CO.,LTD
3
24C02 / 24C04 / 24C08 / 24C16
Device Operation
CLOCK and DATA TRANSITIONS:
The SDA pin is normally pulled high with an external device. Data on the SDA
pin may change only during SCL low time periods (see to Figure 1 on page 4). Data changes during SCL high periods
will indicate a start or stop condition as defined below.
START CONDITION:
A high-to-low transition of SDA with SCL high is a start condition which must precede any other
command (see to Figure 2 on page 4).
STOP CONDITION:
A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop
command will place the EEPROM in a standby power mode (see Figure 2 on page 4).
ACKNOWLEDGE:
All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The
EEPROM sends a "0" to acknowledge that it has received each word. This happens during the ninth clock cycle.
STANDBY MODE:
The
24C02/ 24C04/ 24C08/ 24C16 features a low-power standby mode which is enabled: (a)
upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations
MEMORY RESET:
After an interruption in protocol, power loss or system reset, any two-wire part can be reset by
following these steps:
1.
2.
3.
Clock up to 9 cycles.
Look for SDA high in each cycle while SCL is high.
Create a start condition.
¡
Figure 1: Data Validity
SDA
SCL
DATA STABLE
DATA
CHANGE
DATA STABLE
¡
Figure 2: Start and Stop Definition
SDA
SCL
START
STOP
BEIJING ESTEK ELECTRONICS CO.,LTD
4
24C02 / 24C04 / 24C08 / 24C16
¡
Figure 3: Output Acknowledge
SCL
1
8
9
DATA IN
DATA OUT
START
ACKNOWLEDGE
Device Addressing
The 2K, 4K, 8K and 16K EEPROM devices all require an 8-bit device address word following a start condition to enable
the chip for a read or write operation (see to Figure 4 on page 7).
The device address word consists of a mandatory "1", "0" sequence for the first four most significant bits as shown.
This is common to all the Serial EEPROM devices.
The next 3 bits are the A2, A1 and A0 device address bits for the 2K EEPROM. These 3 bits must compare to their
corresponding hardwired input pins.
The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory page address bit. The
two device address bits must compare to their corresponding hardwired input pins. The A0 pin is no connect.
The 8K EEPROM only uses the A2 device address bit with the next 2 bits being for memory page addressing. The A2 bit
must compare to its corresponding hard-wired input pin. The A1 and A0 pins are no connect.
The 16K does not use any device address bits but instead the 3 bits are used for memory page addressing. These page
addressing bits on the 4K, 8K and 16K devices should be considered the most significant bits of the data word address
which follows. The A0, A1 and A2 pins are no connect.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high
and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the chip will return to a
standby state.
BEIJING ESTEK ELECTRONICS CO.,LTD
5
京公网安备 11010802033920号
EEWORLD
