PCA9545A
4-channel I
2
C switch with interrupt logic and reset
Rev. 03 — 3 March 2005
Product data sheet
1. General description
The PCA9545A is a quad bi-directional translating switch controlled via the I
2
C-bus. The
SCL/SDA upstream pair fans out to four downstream pairs, or channels. Any individual
SCx/SDx channel or combination of channels can be selected, determined by the
contents of the programmable control register. Four interrupt inputs, INT0 to INT3, one for
each of the downstream pairs, are provided. One interrupt output, INT, acts as an AND of
the four interrupt inputs.
An active LOW reset input allows the PCA9545A to recover from a situation where one of
the downstream I
2
C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets the
I
2
C-bus state machine and causes all the channels to be deselected as does the internal
Power-on reset function.
The pass gates of the switches are constructed such that the V
DD
pin can be used to limit
the maximum high voltage which will be passed by the PCA9545A. This allows the use of
different bus voltages on each pair, so that 1.8 V or 2.5 V or 3.3 V parts can communicate
with 5 V parts without any additional protection. External pull-up resistors pull the bus up
to the desired voltage level for each channel. All I/O pins are 5 V tolerant.
2. Features
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
1-of-4 bi-directional translating switches
I
2
C-bus interface logic; compatible with SMBus standards
4 active LOW interrupt inputs
Active LOW interrupt output
Active LOW reset input
2 address pins allowing up to 4 devices on the I
2
C-bus
Channel selection via I
2
C-bus, in any combination
Power-up with all switch channels deselected
Low R
on
switches
Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses
No glitch on power-up
Supports hot insertion
Low stand-by current
Operating power supply voltage range of 2.3 V to 5.5 V
5 V tolerant Inputs
0 kHz to 400 kHz clock frequency
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
s
Latch-up protection exceeds 100 mA per JESD78
Philips Semiconductors
PCA9545A
4-channel I
2
C switch with interrupt logic and reset
s
Three packages offered: SO20, TSSOP20, and HVQFN20
3. Ordering information
Table 1:
Ordering information
T
amb
= –40
°
C to +85
°
C
Type number
PCA9545ABS
PCA9545AD
PCA9545APW
Package
Name
HVQFN20
SO20
TSSOP20
Description
Version
plastic thermal enhanced very thin quad flat package; SOT662-1
no leads; 20 terminals; body 5
×
5
×
0.85 mm
plastic small outline package; 20 leads;
body width 7.5 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT163-1
SOT360-1
Standard packing quantities and other packaging data are available at
www.standardproducts.philips.com/packaging.
4. Marking
Table 2:
Marking codes
Topside mark
9545A
PCA9545AD
PA9545A
Type number
PCA9545ABS
PCA9545AD
PCA9545APW
9397 750 14311
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 3 March 2005
2 of 27
Philips Semiconductors
PCA9545A
4-channel I
2
C switch with interrupt logic and reset
5. Block diagram
PCA9545A
SC0
SC1
SC2
SC3
SD0
SD1
SD2
SD3
V
SS
V
DD
RESET
SWITCH CONTROL LOGIC
POWER-ON
RESET
SCL
SDA
INPUT
FILTER
I
2
C-BUS
CONTROL
A0
A1
INT0
to
INT3
INTERRUPT LOGIC
INT
002aab168
Fig 1. Block diagram of PCA9545A
9397 750 14311
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 3 March 2005
3 of 27
Philips Semiconductors
PCA9545A
4-channel I
2
C switch with interrupt logic and reset
6. Pinning information
6.1 Pinning
A0
A1
RESET
INT0
SD0
SC0
INT1
SD1
SC1
1
2
3
4
5
6
7
8
9
20 V
DD
19 SDA
18 SCL
17 INT
16 SC3
15 SD3
14 INT3
13 SC2
12 SD2
11 INT2
002aab165
A0
A1
RESET
INT0
SD0
SC0
INT1
SD1
SC1
1
2
3
4
5
6
7
8
9
20 V
DD
19 SDA
18 SCL
17 INT
16 SC3
15 SD3
14 INT3
13 SC2
12 SD2
11 INT2
002aab166
PCA9545AD
PCA9545APW
V
SS
10
V
SS
10
Fig 2. Pin configuration for SO20
20 A1
19 A0
terminal 1
index area
Fig 3. Pin configuration for TSSOP20
17 SDA
16 SCL
15 INT
14 SC3
13 SD3
12 INT3
11 SC2
SD2 10
6
7
8
V
SS
9
INT2
18 V
DD
RESET
INT0
SD0
SC0
INT1
1
2
3
4
5
PCA9545ABS
SD1
SC1
002aab167
Transparent top view
Fig 4. Pin configuration for HVQFN20 (transparent top view)
6.2 Pin description
Table 3:
Symbol
A0
A1
RESET
INT0
SD0
SC0
INT1
SD1
9397 750 14311
Pin description
Pin
SO, TSSOP
1
2
3
4
5
6
7
8
HVQFN
19
20
1
2
3
4
5
6
address input 0
address input 1
active LOW reset input
active LOW interrupt input 0
serial data 0
serial clock 0
active LOW interrupt input 1
serial data 1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Description
Product data sheet
Rev. 03 — 3 March 2005
4 of 27
Philips Semiconductors
PCA9545A
4-channel I
2
C switch with interrupt logic and reset
Pin description
…continued
Pin
SO, TSSOP
HVQFN
7
8
[1]
9
10
11
12
13
14
15
16
17
18
serial clock 1
supply ground
active LOW interrupt input 2
serial data 2
serial clock 2
active LOW interrupt input 3
serial data 3
serial clock 3
active LOW interrupt output
serial clock line
serial data line
supply voltage
9
10
11
12
13
14
15
16
17
18
19
20
Description
Table 3:
Symbol
SC1
V
SS
INT2
SD2
SC2
INT3
SD3
SC3
INT
SCL
SDA
V
DD
[1]
HVQFN package die supply ground is connected to both the V
SS
pin and the exposed center pad. The V
SS
pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and
board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the PCB in the thermal pad region.
7. Functional description
Refer to
Figure 1 “Block diagram of PCA9545A” on page 3.
7.1 Device address
Following a START condition, the bus master must output the address of the slave it is
accessing. The address of the PCA9545A is shown in
Figure 5.
To conserve power, no
internal pull-up resistors are incorporated on the hardware selectable address pins and
they must be pulled HIGH or LOW.
1
1
1
fixed
0
0
A1
A0 R/W
hardware
selectable
002aab169
Fig 5. Slave address
The last bit of the slave address defines the operation to be performed. When set to
logic 1, a read is selected while a logic 0 selects a write operation.
9397 750 14311
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 3 March 2005
5 of 27
京公网安备 11010802033920号
EEWORLD
