Three PLLs with deep reference, feedback, and post
dividers to provide precision clock frequencies
Multiple outputs provide several clocking options
Suspend feature shuts down a selection of PLLs and
outputs for power conservation
Outputs may be tristated for board testing
S0 and S1 frequency select inputs modify output fre-
quencies for design flexibility
Glitch-free slewing of CLK_CPU output enables
downstream PLLs to remain locked
5V to 3.3V operation
Accepts 5 to 30MHz crystals
Custom frequency patterns, pinouts, and packages
are available. Contact your local AMI Sales Repre-
sentative for more information.
The FS6322 is a ROM-based CMOS clock generator IC
designed to minimize cost and component count in a va-
riety of electronic systems.
Three low-jitter phase-locked loops (PLLs) drive up to five
low-skew clock outputs to provide a high degree of flexi-
bility. A buffered copy of the reference clock is also avail-
able. The device is packaged in a 16-pin SOIC to mini-
mize board space.
Figure 1: Pin Configuration
CLK_C
VDD
VSS
XIN
XOUT
XBUF
CLK_D
CLK_CPU
1
2
3
16
15
14
OE
SUSPEND#
VDD
S1
S0
VSS
CLK_A
CLK_B
FS6322
4
5
6
7
8
13
12
11
10
9
16-pin (0.150”) SOIC
Figure 2: Block Diagram
OE
XIN
XOUT
Crystal
Oscillator
PLL A
XBUF
CLK_A
CLK_B
PLL B
Clock
Logic
CLK_C
CLK_D
CLK_CPU
S1:S0
SUSPEND#
PLL CPU
FS6322
This document contains information on a product under development. American Microsystems, Inc. reserves the right to change or discontinue this product without notice.
ISO9001
3.1.02
FS6322-02
Three-PLL Clock Generator IC
Table 1: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI
U
= Input with Internal Pull-Up; DI
D
= Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active Low pin
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TYPE
DO
P
P
AI
AO
DO
DO
DO
DO
DO
P
DI
DI
P
DI
DI
NAME
CLK_C
VDD
VSS
XIN
XOUT
XBUF
CLK_D
CLK_CPU
CLK_A
CLK_B
VSS
S0
S1
VDD
SUSPEND#
OE
C clock output
Power supply (5V to 3.3V)
Ground
Crystal oscillator feedback
Crystal oscillator drive
DESCRIPTION
Buffered crystal oscillator frequency output
D clock output
CPU PLL output with controlled frequency slew rate
A clock output
B clock output
Ground
Frequency select control input for the CLK_CPU output
Frequency select control input for the CLK_CPU output
Power supply (5V to 3.3V)
Active-low control input powers-down selected PLLs and outputs
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at
these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance,
functionality, and reliability.
PARAMETER
Supply Voltage, dc (V
SS
= ground)
Input Voltage, dc
Output Voltage, dc
Input Clamp Current, dc (V
I
< 0 or V
I
> V
DD
)
Output Clamp Current, dc (V
I
< 0 or V
I
> V
DD
)
Storage Temperature Range (non-condensing)
Ambient Temperature Range, Under Bias
Junction Temperature
Lead Temperature (soldering, 10s)
Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7)
SYMBOL
V
DD
V
I
V
O
I
IK
I
OK
T
S
T
A
T
J
MIN.
V
SS
-0.5
V
SS
-0.5
V
SS
-0.5
-50
-50
-65
-55
MAX.
7
V
DD
+0.5
V
DD
+0.5
50
50
150
125
150
260
2
UNITS
V
V
V
mA
mA
°C
°C
°C
°C
kV
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy elec-
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