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CY7C331-30TMB

Description
Asynchronous Registered EPLD
File Size425KB,18 Pages
ManufacturerCypress Semiconductor
Download Datasheet View All

CY7C331-30TMB Overview

Asynchronous Registered EPLD

1CY7C331
fax id: 6016
CY7C331
Asynchronous Registered EPLD
Features
• Twelve I/O macrocells each having:
— One state flip-flop with an XOR sum-of-products
input
— One feedback flip-flop with input coming from the
I/O pin
— Independent (product term) set, reset, and clock in-
puts on all registers
— Asynchronous bypass capability on all registers un-
der product term control (r = s = 1)
— Global or local output enable on three-state I/O
— Feedback from either register to the array
192 product terms with variable distribution to macro-
cells
13 inputs, 12 feedback I/O pins, plus 6 shared I/O mac-
rocell feedbacks for a total of 31 true and complemen-
tary inputs
High speed: 20 ns maximum t
PD
Security bit
Space-saving 28-pin slim-line DIP package; also avail-
able in 28-pin PLCC
• Low power
— 90 mA typical I
CC
quiescent
— 180 mA I
CC
maximum
— UV-erasable and reprogrammable
— Programming and operation 100% testable
Functional Description
The CY7C331 is the most versatile PLD available for asyn-
chronous designs. Central resources include twelve full D-type
flip-flops with separate set, reset, and clock capability. For in-
creased utility, XOR gates are provided at the D-inputs and the
product term allocation per flip-flop is variably distributed.
I/O Resources
Pins 1 through 7 and 9 through 14 serve as array inputs; pin
14 may also be used as a global output enable for the I/O
macrocell three-state outputs. Pins 15 through 20 and 23
through 28 are connected to I/O macrocells and may be man-
aged as inputs or outputs depending on the configuration and
the macrocell OE terms.
Logic Block Diagram
OE/I
12
14
I
11
13
I
10
12
I
9
11
I
8
10
I
7
9
GND
8
I
6
7
I
5
6
I
4
5
I
3
4
I
2
3
I
1
2
I
0
1
PROGRAMMABLE AND ARRAY
(192x62)
4
12
6
10
8
8
8
8
10
6
12
4
15
I/O
11
16
I/O
10
17
I/O
9
18
I/O
8
19
I/O
7
20
I/O
6
21
GND
22
V
CC
23
I/O
5
24
I/O
4
25
I/O
3
26
I/O
2
27
I/O
1
28
I/O
0
C331–1
Cypress Semiconductor Corporation
3901 North First Street
San Jose • CA 95134 • 408-943-2600
January 1989 – Revised December 1992

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