Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature .................................. –65°C to +150°C
Ambient temperature with
power applied ............................................. –55°C to +125°C
Supply voltage to ground potential ...............–0.5 V to +7.0 V
DC voltage applied to outputs
in High Z State
[2]
...........................................–0.5 V to +7.0 V
DC input voltage
[2]
........................................–0.5 V to +7.0 V
Output current into outputs (LOW) .............................. 20 mA
Range
Commercial
Industrial
Static discharge voltage........................................... >2001 V
(per MIL-STD-883, Method 3015)
Latch-up current ..................................................... >200 mA
Operating Range
Ambient
Temperature
0
°
C to +70
°
C
–40
°
C to +85
°
C
V
CC
5 V
±
10%
5 V
±
10%
Electrical Characteristics
Over the Operating Range
–15
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
Description
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
Input LOW
Voltage
[2]
Input Leakage
Current
Output Leakage
Current
V
CC
Operating
Supply Current
Automatic
Power-down
Current
Automatic
Power-down
Current
Test Conditions
V
CC
= Min.,
I
OH
= –4.0 mA
V
CC
= Min.,
I
OL
= 8.0 mA
Min
2.4
Max
Min
2.4
–20
Max
Min
2.4
–35
Max
Unit
V
V
V
V
μA
μA
mA
mA
0.4
2.2
–0.5
V
CC
+ 0.3
V
0.8
+5
+5
130
40
2.2
–0.5
–5
–5
0.4
V
CC
+ 0.3 V
0.8
+5
+5
110
20
2.2
–0.5
–5
–5
0.4
V
CC
+ 0.3 V
0.8
+5
+5
100
20
GND
≤
V
I
≤
V
CC
GND
≤
V
I
≤
V
CC
,
Output Disabled
V
CC
= Max.,
I
OUT
= 0 mA
Max. V
CC
,
CE
1
≥
V
IH
or CE
2
≤
V
IL
Min. Duty Cycle =100%
Max. V
CC
,
CE
1
≥
V
CC
– 0.3 V,
or CE
2
≤
0.3 V
V
IN
≥
V
CC
– 0.3 V or
V
IN
≤
0.3 V
–5
–5
I
SB2
15
15
15
mA
Document #: 38-05043 Rev. *E
Page 3 of 15
[+] Feedback
CY7C185
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0 V
Max
7
7
Unit
pF
pF
Figure 1. AC Test Loads and Waveforms
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R1 481
Ω
5V
OUTPUT
5 pF
INCLUDING
JIGAND
SCOPE
R1 481
Ω
3.0 V
R2
255Ω
GND
10%
ALL INPUT PULSES
90%
90%
10%
≤
5 ns
R2
255Ω
≤
5 ns
Equivalent to:
OUTPUT
(a)
(b)
THÉVENIN EQUIVALENT
167Ω
1.73 V
Notes
2. Minimum voltage is equal to –3.0 V for pulse durations less than 30 ns.
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05043 Rev. *E
Page 4 of 15
[+] Feedback
CY7C185
Switching Characteristics
Over the Operating Range
[4]
-15
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE1
t
ACE2
t
DOE
t
LZOE
t
HZOE
t
LZCE1
t
LZCE2
t
HZCE
t
PU
t
PD
Write Cycle
[7]
t
WC
t
SCE1
t
SCE2
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
CE
1
LOW to Write End
CE
2
HIGH to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE LOW to High Z
[5]
WE HIGH to Low Z
3
15
12
12
12
0
0
12
8
0
7
5
20
15
15
15
0
0
15
10
0
7
5
35
20
20
25
0
0
20
12
0
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW to Data Valid
CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High
Z
[5]
[6]
-20
Max
Min
20
15
20
5
15
15
8
20
20
9
3
7
8
5
3
7
8
0
15
20
0
5
3
3
5
Max
Min
35
-35
Max
Unit
ns
35
35
35
15
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
ns
ns
20
ns
Description
Min
15
3
3
3
3
CE
1
LOW to Low Z
CE
2
HIGH to Low Z
CE
1
HIGH to High Z
[5, 6]
CE
2
LOW to High Z
CE
1
LOW to Power-up
CE
2
to HIGH to Power-up
CE
1
HIGH to Power-down
CE
2
LOW to Power-down
0
Notes
4. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified I
OL
/I
OH
and 30-pF load capacitance.
5. t
HZOE,
t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured
±500
mV from steady state voltage.
6. At any temperature and voltage condition, t
HZCE
is less than t
LZCE1
and t
LZCE2
for any given device.
7. The internal write time of the memory is defined by the overlap of CE
1
LOW, CE
2
HIGH, and WE LOW. All 3 signals must be active to initiate a write and either signal
can terminate a write by going HIGH. The data input setup and hold timing must be referenced to the rising edge of the signal that terminates the write.
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