CY14B104LA, CY14B104NA
4-Mbit (512 K × 8/256 K × 16) nvSRAM
4-Mbit (512 K × 8/256 K × 16) nvSRAM
Features
■
■
■
■
■
■
■
■
■
■
■
20 ns, 25 ns, and 45 ns access times
Internally organized as 512 K × 8 (CY14B104LA) or 256 K × 16
(CY14B104NA)
Hands off automatic STORE on power-down with only a small
capacitor
STORE to QuantumTrap non-volatile elements initiated by
software, device pin, or AutoStore on power-down
RECALL to SRAM initiated by software or power-up
Infinite read, write, and recall cycles
1 million STORE cycles to QuantumTrap
20 year data retention
Single 3 V +20, –10 operation
Industrial temperature
■
Packages
❐
44-/54-pin thin small outline package (TSOP) Type II
❐
48-ball fine-pitch ball grid array (FBGA)
Pb-free and restriction of hazardous substances (RoHS)
compliant
Functional Description
The Cypress CY14B104LA/CY14B104NA is a fast static RAM
(SRAM), with a non-volatile element in each memory cell. The
memory is organized as 512 K bytes of 8 bits each or 256 K
words of 16 bits each. The embedded non-volatile elements
incorporate QuantumTrap technology, producing the world’s
most reliable non-volatile memory. The SRAM provides infinite
read and write cycles, while independent non-volatile data
resides in the highly reliable QuantumTrap cell. Data transfers
from the SRAM to the non-volatile elements (the STORE
operation) takes place automatically at power-down. On
power-up, data is restored to the SRAM (the RECALL operation)
from the non-volatile memory. Both the STORE and RECALL
operations are also available under software control.
V
CC
V
CAP
Logic Block Diagram
[1, 2, 3]
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
17
A
18
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
DQ
8
DQ
9
DQ
10
DQ
11
DQ
12
DQ
13
DQ
14
DQ
15
I
N
P
U
T
B
U
F
F
E
R
S
R
O
W
D
E
C
O
D
E
R
Quatrum Trap
2048 X 2048
STORE
RECALL
STATIC RAM
ARRAY
2048 X 2048
POWER
CONTROL
STORE/RECALL
CONTROL
HSB
SOFTWARE
DETECT
A
14
- A
2
COLUMN I/O
COLUMN DEC
OE
WE
CE
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
BLE
BHE
Notes
1. Address A
0
–A
18
for × 8 configuration and Address A
0
–A
17
for × 16 configuration.
2. Data DQ
0
–DQ
7
for × 8 configuration and Data DQ
0
–DQ
15
for × 16 configuration.
3. BHE and BLE are applicable for × 16 configuration only.
Cypress Semiconductor Corporation
Document #: 001-49918 Rev. *I
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised July 12, 2011
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CY14B104LA, CY14B104NA
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 4
Device Operation .............................................................. 5
SRAM Read ....................................................................... 5
SRAM Write ....................................................................... 5
AutoStore Operation ........................................................ 5
Hardware STORE Operation ............................................ 5
Hardware RECALL (Power-Up) ....................................... 6
Software STORE ............................................................... 6
Software RECALL ............................................................. 6
Preventing AutoStore ....................................................... 7
Data Protection ................................................................. 7
Noise Considerations ....................................................... 7
Best Practices ................................................................... 8
Maximum Ratings ............................................................. 9
Operating Range ............................................................... 9
DC Electrical Characteristics .......................................... 9
Data Retention and Endurance ..................................... 10
Capacitance .................................................................... 10
Thermal Resistance ........................................................ 10
AC Test Loads ................................................................ 10
AC Test Conditions ........................................................ 10
AC Switching Characteristics ....................................... 11
Switching Waveforms .................................................... 11
AutoStore/Power-Up RECALL ....................................... 14
Switching Waveforms .................................................... 14
Software Controlled STORE/RECALL Cycle ................ 15
Switching Waveforms .................................................... 15
Hardware STORE Cycle ................................................. 16
Switching Waveforms .................................................... 16
Truth Table For SRAM Operations ................................ 17
Ordering Information ...................................................... 18
Ordering Code Definitions ......................................... 19
Package Diagrams .......................................................... 20
Acronyms ........................................................................ 23
Document Conventions ............................................. 23
Units of Measure ....................................................... 23
Document History Page ................................................. 24
Sales, Solutions, and Legal Information ...................... 25
Worldwide Sales and Design Support ....................... 25
Products .................................................................... 25
PSoC Solutions ......................................................... 25
Document #: 001-49918 Rev. *I
Page 2 of 25
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CY14B104LA, CY14B104NA
Pinouts
Figure 1. Pin Diagram – 48-ball FBGA
48-ball FBGA
(× 8)
Top View
(not to scale)
1
NC
NC
DQ
0
V
SS
V
CC
DQ
3
NC
A
18
2
OE
NC
NC
DQ
1
DQ
2
NC
HSB
A
8
3
A
0
A
3
A
5
A
17
V
CAP
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
NC
DQ
5
DQ
6
NC
WE
A
11
6
NC
NC
DQ
4
V
CC
V
SS
DQ
7
NC
NC
[4]
48-ball FBGA
(× 16)
Top View
(not to scale)
1
A
B
C
D
E
F
G
H
2
OE
BHE
3
A
0
A
3
A
5
A
17
V
CAP
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
DQ
1
DQ
3
DQ
4
DQ
5
WE
A
11
6
NC
DQ
0
DQ
2
V
CC
V
SS
DQ
6
DQ
7
NC
A
B
C
D
E
F
G
H
BLE
DQ
8
DQ
9
DQ
10
V
SS
DQ
11
V
CC
DQ
12
DQ
14
DQ
13
DQ
15
HSB
NC
[4]
A
8
Figure 2. Pin Diagram – 44-pin TSOP II
(× 8)
NC
[5]
NC
A
0
A
1
A
2
A
3
A
4
CE
DQ
0
DQ
1
V
CC
V
SS
DQ
2
DQ
3
WE
A
5
A
6
A
7
A
8
A
9
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
HSB
NC
[4]
NC
A
18
A
17
A
16
A
15
OE
DQ
7
DQ
6
V
SS
V
CC
DQ
5
DQ
4
V
CAP
A
14
A
13
A
12
A
11
A
10
NC
NC
(× 16)
A
0
A
1
A
2
A
3
A
4
CE
DQ
0
DQ
1
DQ
2
DQ
3
V
CC
V
SS
DQ
4
DQ
5
DQ
6
DQ
7
WE
A
5
A
6
A
7
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
[6]
44-pin TSOP II
(× 8)
44-pin TSOP II
(× 16)
Top View
(not to scale)
Top View
(not to scale)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
17
A
16
A
15
OE
BHE
BLE
DQ
15
DQ
14
DQ
13
DQ
12
V
SS
V
CC
DQ
11
DQ
10
DQ
9
DQ
8
V
CAP
A
14
A
13
A
12
A
11
A
10
Notes
4. Address expansion for 8-Mbit. NC pin not connected to die.
5. Address expansion for 16-Mbit. NC pin not connected to die.
6. HSB pin is not available in 44-pin TSOP II (× 16) package.
Document #: 001-49918 Rev. *I
Page 3 of 25
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CY14B104LA, CY14B104NA
Pinouts
(continued)
Figure 3. Pin Diagram – 54-pin TSOP II (× 16)
NC
[7]
NC
A
0
A
1
A
2
A
3
A
4
CE
DQ
0
DQ
1
DQ
2
DQ
3
V
CC
V
SS
DQ
4
DQ
5
DQ
6
DQ
7
WE
A
5
A
6
A
7
A
8
A
9
NC
NC
NC
54
1
53
2
52
3
51
4
50
5
49
6
48
7
47
8
46
9
45
10
54-pin TSOP II
44
11
(
×
16)
43
12
42
13
Top View
41
14
(
not to scale)
40
15
39
16
38
17
37
18
36
19
35
20
34
21
33
22
32
23
31
24
30
25
29
26
27
28
HSB
NC
[8]
A
17
A
16
A
15
OE
BHE
BLE
DQ
15
DQ
14
DQ
13
DQ
12
V
SS
V
CC
DQ
11
DQ
10
DQ
9
DQ
8
V
CAP
A
14
A
13
A
12
A
11
A
10
NC
NC
NC
Pin Definitions
Pin Name
I/O Type
Description
Input
Address inputs.
Used to select one of the 524,288 bytes of the nvSRAM for × 8 Configuration.
A
0
–A
18
A
0
–A
17
Address inputs.
Used to Select one of the 262,144 words of the nvSRAM for × 16 Configuration.
DQ
0
–DQ
7
Input/Output
Bidirectional data I/O lines for × 8 configuration.
Used as input or output lines depending on operation.
Bidirectional data I/O lines for × 16 configuration.
Used as input or output lines depending on
DQ
0
–DQ
15
operation.
Input
Write Enable input, Active LOW.
When selected LOW, data on the I/O pins is written to the specific
WE
address location.
Input
Chip Enable input, Active LOW.
When LOW, selects the chip. When HIGH, deselects the chip.
CE
Input
Output Enable, Active LOW.
The active LOW OE input enables the data output buffers during read
OE
cycles. I/O pins are tristated on deasserting OE HIGH.
Input
Byte High Enable, Active LOW.
Controls DQ
15
–DQ
8
.
BHE
Input
Byte Low Enable, Active LOW.
Controls DQ
7
–DQ
0
.
BLE
Ground
Ground for the device.
Must be connected to the ground of the system.
V
SS
V
CC
Power supply
Power supply inputs to the device.
Input/Output
Hardware STORE Busy (HSB).
When LOW this output indicates that a Hardware STORE is in progress.
HSB
[9]
When pulled LOW external to the chip it initiates a non-volatile STORE operation. After each Hardware
and Software STORE operation, HSB is driven HIGH for a short time (t
HHHD
) with standard output high
current, and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection
optional).
V
CAP
Power supply
AutoStore Capacitor.
Supplies power to the nvSRAM during power loss to store data from SRAM to
non-volatile elements.
NC
No connect
No Connect.
This pin is not connected to the die.
Notes
7. Address expansion for 16-Mbit. NC pin not connected to die.
8. Address expansion for 8-Mbit. NC pin not connected to die.
9. HSB pin is not available in 44-pin TSOP II (× 16) package.
Document #: 001-49918 Rev. *I
Page 4 of 25
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CY14B104LA, CY14B104NA
Device Operation
The CY14B104LA/CY14B104NA nvSRAM is made up of two
functional components paired in the same physical cell. They are
a SRAM memory cell and a non-volatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the non-volatile cell (the STORE
operation), or from the non-volatile cell to the SRAM (the
RECALL operation). Using this unique architecture, all cells are
stored and recalled in parallel. During the STORE and RECALL
operations, SRAM read and write operations are inhibited. The
CY14B104LA/CY14B104NA supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the non-volatile cells and up to 1 million STORE
operations. Refer to the
Truth Table For SRAM Operations on
page 17
for a complete description of read and write modes.
automatically disconnects the V
CAP
pin from V
CC
. A STORE
operation is initiated with power provided by the V
CAP
capacitor.
Note
If the capacitor is not connected to V
CAP
pin, AutoStore
must be disabled using the soft sequence specified in
Preventing
AutoStore on page 7.
In case AutoStore is enabled without a
capacitor on V
CAP
pin, the device attempts an AutoStore
operation without sufficient charge to complete the Store. This
corrupts the data stored in nvSRAM.
Figure 4
shows the proper connection of the storage capacitor
(V
CAP
) for automatic store operation. Refer to
DC Electrical
Characteristics on page 9
for the size of V
CAP
. The voltage on
the V
CAP
pin is driven to V
CC
by a regulator on the chip. A pull-up
should be placed on WE to hold it inactive during power-up. This
pull-up is effective only if the WE signal is tristate during
power-up. Many MPUs tristate their controls on power-up. This
should be verified when using the pull-up. When the nvSRAM
comes out of power-on-RECALL, the MPU must be active or the
WE held inactive until the MPU comes out of reset.
To reduce unnecessary non-volatile stores, AutoStore and
hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
Figure 4. AutoStore Mode
V
CC
SRAM Read
The CY14B104LA/CY14B104NA performs a read cycle when
CE and OE are LOW and WE and HSB are HIGH. The address
specified on pins A
0–18
or A
0–17
determines which of the 524,288
data bytes or 262,144 words of 16 bits each are accessed. Byte
enables (BHE, BLE) determine which bytes are enabled to the
output, in the case of 16-bit words. When the read is initiated by
an address transition, the outputs are valid after a delay of t
AA
(read cycle 1). If the read is initiated by CE or OE, the outputs
are valid at t
ACE
or at t
DOE
, whichever is later (read cycle 2). The
data output repeatedly responds to address changes within the
t
AA
access time without the need for transitions on any control
input pins. This remains valid until another address change or
until CE or OE is brought HIGH, or WE or HSB is brought LOW.
SRAM Write
10 kOhm
0.1 uF
V
CC
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins DQ
0–15
are written into the memory if the data is valid (t
SD
time) before
the end of a WE controlled write or before the end of an CE
controlled write. The Byte Enable inputs (BHE, BLE) determine
which bytes are written, in the case of 16-bit words. It is recom-
mended that OE be kept HIGH during the entire write cycle to
avoid data bus contention on common I/O lines. If OE is left LOW,
internal circuitry turns off the output buffers t
HZWE
after WE goes
LOW.
WE
V
CAP
V
CAP
V
SS
AutoStore Operation
The CY14B104LA/CY14B104NA stores data to the nvSRAM
using one of the following three storage operations: Hardware
STORE activated by the HSB; Software STORE activated by an
address sequence; AutoStore on device power-down. The
AutoStore operation is a unique feature of QuantumTrap
technology
and
is
enabled
by
default
on
the
CY14B104LA/CY14B104NA.
During a normal operation, the device draws current from V
CC
to
charge a capacitor connected to the V
CAP
pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
CC
pin drops below V
SWITCH
, the part
Note
10. HSB pin is not available in 44-pin TSOP II (× 16) package.
Hardware STORE Operation
The CY14B104LA/CY14B104NA provides the HSB
[10]
pin to
control and acknowledge the STORE operations. The HSB pin
is used to request a hardware STORE cycle. When the HSB pin
is driven LOW, the CY14B104LA/CY14B104NA conditionally
initiates a STORE operation after t
DELAY
. An actual STORE cycle
only begins if a write to the SRAM has taken place since the last
STORE or RECALL cycle. The HSB pin also acts as an open
drain driver (internal 100 k weak pull-up resistor) that is inter-
nally driven LOW to indicate a busy condition when the STORE
(initiated by any means) is in progress.
Note
After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (t
HHHD
) with standard output high
current and then remains HIGH by internal 100 k pull-up
resistor.
Document #: 001-49918 Rev. *I
Page 5 of 25
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