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W971GG6JB-25I

Description
DDR DRAM, 64MX16, 0.4ns, CMOS, PBGA84, 8 X 12.50 MM, ROHS COMPLIANT, WBGA-84
Categorystorage    storage   
ManufacturerWinbond Electronics Corporation
Websitehttp://www.winbond.com.tw
Environmental Compliance
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W971GG6JB-25I Overview

DDR DRAM, 64MX16, 0.4ns, CMOS, PBGA84, 8 X 12.50 MM, ROHS COMPLIANT, WBGA-84

W971GG6JB-25I Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerWinbond Electronics Corporation
Parts packaging codeBGA
package instructionTFBGA, BGA84,9X15,32
Contacts84
Reach Compliance Codecompliant
ECCN codeEAR99
access modeMULTI BANK PAGE BURST
Maximum access time0.4 ns
Other featuresAUTO/SELF REFRESH
Maximum clock frequency (fCLK)400 MHz
I/O typeCOMMON
interleaved burst length4,8
JESD-30 codeR-PBGA-B84
length12.5 mm
memory density1073741824 bit
Memory IC TypeDDR DRAM
memory width16
Number of functions1
Number of ports1
Number of terminals84
word count67108864 words
character code64000000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize64MX16
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTFBGA
Encapsulate equivalent codeBGA84,9X15,32
Package shapeRECTANGULAR
Package formGRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply1.8 V
Certification statusNot Qualified
refresh cycle8192
Maximum seat height1.2 mm
self refreshYES
Continuous burst length4,8
Maximum standby current0.01 A
Maximum slew rate0.225 mA
Maximum supply voltage (Vsup)1.9 V
Minimum supply voltage (Vsup)1.7 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
width8 mm
Base Number Matches1
W971GG6JB
8M
8 BANKS
16 BIT DDR2 SDRAM
Table of Contents-
1.
2.
3.
4.
5.
6.
7.
8.
8.1
8.2
GENERAL DESCRIPTION ................................................................................................................... 4
FEATURES ........................................................................................................................................... 4
ORDER INFORMATION ....................................................................................................................... 5
KEY PARAMETERS ............................................................................................................................. 5
BALL CONFIGURATION ...................................................................................................................... 6
BALL DESCRIPTION ............................................................................................................................ 7
BLOCK DIAGRAM ................................................................................................................................ 8
FUNCTIONAL DESCRIPTION .............................................................................................................. 9
Power-up and Initialization Sequence ................................................................................................... 9
Mode Register and Extended Mode Registers Operation ................................................................... 10
8.2.1
8.2.2
8.2.2.1
8.2.2.2
8.2.2.3
8.2.2.4
8.2.3
8.2.3.1
8.2.3.2
8.2.3.3
8.2.4
8.2.5
8.2.5.1
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
8.3.8
8.3.9
8.3.10
8.3.11
8.4
Mode Register Set Command (MRS)............................................................................... 10
Extend Mode Register Set Commands (EMRS) .............................................................. 11
Extend Mode Register Set Command (1), EMR (1) ................................................ 11
DLL Enable/Disable ................................................................................................ 12
Extend Mode Register Set Command (2), EMR (2) ................................................ 13
Extend Mode Register Set Command (3), EMR (3) ................................................ 14
Off-Chip Driver (OCD) Impedance Adjustment ................................................................ 15
Extended Mode Register for OCD Impedance Adjustment .................................... 16
OCD Impedance Adjust .......................................................................................... 16
Drive Mode ............................................................................................................. 17
On-Die Termination (ODT) ............................................................................................... 18
ODT related timings ......................................................................................................... 18
MRS command to ODT update delay ..................................................................... 18
Bank Activate Command .................................................................................................. 20
Read Command ............................................................................................................... 21
Write Command ............................................................................................................... 21
Burst Read with Auto-precharge Command ..................................................................... 21
Burst Write with Auto-precharge Command ..................................................................... 21
Precharge All Command .................................................................................................. 21
Self Refresh Entry Command .......................................................................................... 21
Self Refresh Exit Command ............................................................................................. 22
Refresh Command ........................................................................................................... 22
No-Operation Command .................................................................................................. 23
Device Deselect Command .............................................................................................. 23
Command Function ............................................................................................................................. 20
Read and Write access modes ........................................................................................................... 23
8.4.1
Posted
CAS
.................................................................................................................... 23
-1-
Publication Release Date: Sep. 24, 2013
Revision A09

W971GG6JB-25I Related Products

W971GG6JB-25I W971GG6JB-25A W971GG6JB-25K W971GG6JB-25L
Description DDR DRAM, 64MX16, 0.4ns, CMOS, PBGA84, 8 X 12.50 MM, ROHS COMPLIANT, WBGA-84 DDR DRAM, 64MX16, 0.4ns, CMOS, PBGA84, 8 X 12.50 MM, ROHS COMPLIANT, WBGA-84 DDR DRAM, 64MX16, 0.4ns, CMOS, PBGA84, 8 X 12.50 MM, ROHS COMPLIANT, WBGA-84 DDR DRAM, 64MX16, 0.4ns, CMOS, PBGA84, 8 X 12.50 MM, ROHS COMPLIANT, WBGA-84
Is it Rohs certified? conform to conform to conform to conform to
Maker Winbond Electronics Corporation Winbond Electronics Corporation Winbond Electronics Corporation Winbond Electronics Corporation
Parts packaging code BGA BGA BGA BGA
package instruction TFBGA, BGA84,9X15,32 TFBGA, BGA84,9X15,32 TFBGA, BGA84,9X15,32 TFBGA, BGA84,9X15,32
Contacts 84 84 84 84
Reach Compliance Code compliant compliant compliant compliant
ECCN code EAR99 EAR99 EAR99 EAR99
access mode MULTI BANK PAGE BURST MULTI BANK PAGE BURST MULTI BANK PAGE BURST MULTI BANK PAGE BURST
Maximum access time 0.4 ns 0.4 ns 0.4 ns 0.4 ns
Other features AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH
Maximum clock frequency (fCLK) 400 MHz 400 MHz 400 MHz 400 MHz
I/O type COMMON COMMON COMMON COMMON
interleaved burst length 4,8 4,8 4,8 4,8
JESD-30 code R-PBGA-B84 R-PBGA-B84 R-PBGA-B84 R-PBGA-B84
length 12.5 mm 12.5 mm 12.5 mm 12.5 mm
memory density 1073741824 bit 1073741824 bit 1073741824 bit 1073741824 bit
Memory IC Type DDR DRAM DDR DRAM DDR DRAM DDR DRAM
memory width 16 16 16 16
Number of functions 1 1 1 1
Number of ports 1 1 1 1
Number of terminals 84 84 84 84
word count 67108864 words 67108864 words 67108864 words 67108864 words
character code 64000000 64000000 64000000 64000000
Operating mode SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
Maximum operating temperature 85 °C 95 °C 105 °C 85 °C
Minimum operating temperature -40 °C -40 °C -40 °C -
organize 64MX16 64MX16 64MX16 64MX16
Output characteristics 3-STATE 3-STATE 3-STATE 3-STATE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TFBGA TFBGA TFBGA TFBGA
Encapsulate equivalent code BGA84,9X15,32 BGA84,9X15,32 BGA84,9X15,32 BGA84,9X15,32
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form GRID ARRAY, THIN PROFILE, FINE PITCH GRID ARRAY, THIN PROFILE, FINE PITCH GRID ARRAY, THIN PROFILE, FINE PITCH GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius) NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
power supply 1.8 V 1.8 V 1.8 V 1.8 V
Certification status Not Qualified Not Qualified Not Qualified Not Qualified
refresh cycle 8192 8192 8192 8192
Maximum seat height 1.2 mm 1.2 mm 1.2 mm 1.2 mm
self refresh YES YES YES YES
Continuous burst length 4,8 4,8 4,8 4,8
Maximum standby current 0.01 A 0.01 A 0.01 A 0.007 A
Maximum slew rate 0.225 mA 0.225 mA 0.225 mA 0.225 mA
Maximum supply voltage (Vsup) 1.9 V 1.9 V 1.9 V 1.9 V
Minimum supply voltage (Vsup) 1.7 V 1.7 V 1.7 V 1.7 V
Nominal supply voltage (Vsup) 1.8 V 1.8 V 1.8 V 1.8 V
surface mount YES YES YES YES
technology CMOS CMOS CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL OTHER
Terminal form BALL BALL BALL BALL
Terminal pitch 0.8 mm 0.8 mm 0.8 mm 0.8 mm
Terminal location BOTTOM BOTTOM BOTTOM BOTTOM
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
width 8 mm 8 mm 8 mm 8 mm

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