Cortina Systems
®
LXT6155 155 Mbps
SDH/SONET/ATM Transceiver
Datasheet
The Cortina Systems
®
LXT6155 155 Mbps SDH/SONET/ATM Transceiver (LXT6155 Transceiver) is a
high speed fully integrated transceiver designed for 155 Mbps SDH/SONET/ATM transmission system
applications. The LXT6155 Transceiver provides a LVPECL interface for fiber optics modules, and a CMI
interface for coax cable drive. These circuits are implemented using Cortina Systems, Inc.’s proven low
power 3.3V CMOS analog and digital circuits. The transmitter incorporates a parallel-to-serial converter,
a frequency multiplier PLL, CMI line encoders, and line interfaces for both coax cable and optical fiber.
The receiver incorporates an adaptive equalizer, a clock recovery PLL, Loss of Signal (LOS) detector,
CMI and NRZ decoders, a serial-to-parallel converter, and an SDH/SONET frame byte detector/aligner.
At the system interface, the LXT6155 Transceiver offers both parallel 8-bit and serial differential
interfaces. The LXT6155 Transceiver also operates in either Hardware stand-alone mode or Software
mode. Software mode is controlled by a serial microprocessor (µP) to program formats and operating/
test modes.
Product Features
Complies with:
— Bellcore* SONET GR-253
— ITU-T G.703/813/958 STM1
Two line interface formats:
— Fiber LVPECL NRZ
— Coax CMI
Transmit synthesizer PLL
Receive clock recovery PLL
Adaptive CMI equalizer
Analog circuitry for transformer drive
Programmable LOS function
CMI encoder and decoder
Serial/Parallel and Parallel/Serial conversion
Byte alignment for SDH/SONET frames
Two modes of operation:
— Microprocessor controlled; software mode
— Stand-alone; hardware mode
No external crystal required. A 19.44 MHz
crystal is optional
Low power consumption (less than 760 mW
typical)
Operates from a single 3.3 V supply
64 pin LQFP package
Applications
OC3/STM1 SDH/SONET Cross Connects
OC3/STM1 SDH/SONET Add/Drop Mux
OC3/STM1 Transmission Systems
OC3/STM1 Short Haul Serial Links
OC3/STM1 ATM/WAN Transmission Systems
OC3/STM1 ATM/WAN Access Systems
LXT6155 Transceiver
Datasheet
249612, Revision 7.0
14 Feburary 2007
Legal Disclaimer
This document contains information proprietary to Cortina Systems, Inc. Any use or disclosure, in whole or in part, of
this information to any unauthorized party, for any purposes other than that for which it is provided is expressly
prohibited except as authorized by Cortina Systems, Inc. in writing. Cortina Systems, Inc. reserves its rights to pursue
both civil and criminal penalties for copying or disclosure of this material without authorization.
*Other names and brands may be claimed as the property of others.
© Cortina Systems, Inc. 2007
Cortina Systems
®
LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Page 2
LXT6155 Transceiver
Datasheet
249612, Revision 7.0
14 Feburary 2007
Contents
Contents
1.0
2.0
3.0
LXT6155 Transceiver Block Diagram...........................................................................................8
Pin Assignments and Signal Descriptions.................................................................................. 9
Functional Description................................................................................................................14
3.1
Transmitter..........................................................................................................................14
3.1.1 Transmitted Signal .................................................................................................15
3.1.1.1 Fiber Based G.957/GR-253 Transmission Systems ..............................15
3.1.2 Coax Based G.703/GR-253 Transmission Systems..............................................15
3.1.2.1 CMI Encoding ........................................................................................15
3.1.3 Tx Clock Monitoring ...............................................................................................16
Receiver..............................................................................................................................16
3.2.1 Analog Front End and Timing Recovery ................................................................16
3.2.1.1 CMI Mode ..............................................................................................16
3.2.1.2 NRZ Mode..............................................................................................16
3.2.2 Receive Frame Detect and Byte Alignment ...........................................................17
3.2.2.1 Loss of Signal (LOS)..............................................................................18
3.2.2.2 Coax Interface........................................................................................18
3.2.2.3 Fiber Interface........................................................................................18
Clocks .................................................................................................................................19
3.3.1 Parallel Mode .........................................................................................................19
3.3.1.1 Transmit Parallel Input Clock (TPICLK) .................................................19
3.3.1.2 Receive Parallel Output Clock (RPOCLK) .............................................19
3.3.2 Serial Mode............................................................................................................19
3.3.2.1 Transmit Serial Input Clock (TSICLKP/TSICLKN) .................................19
3.3.2.2 Receive Serial Output Clock (RSOCLKP/RSOCLKN) ...........................19
3.3.3 Crystal Reference Clock (XTALIN/XTALOUT).......................................................20
Jitter ....................................................................................................................................20
3.4.1 Jitter Tolerance ......................................................................................................20
3.4.2 Jitter Generation (Intrinsic Jitter)............................................................................20
3.4.3 Jitter Transfer.........................................................................................................20
Operational Modes .............................................................................................................20
3.5.1 Hardware Mode .....................................................................................................21
3.5.1.1 PLL Clock Reference (CIS pin) ..............................................................21
3.5.1.2 Loopback Test (RLIS and LLIS pins) .....................................................22
3.5.1.3 Line Interface Selection (MODE Pin) .....................................................22
3.5.1.4 Parallel/Serial Mode Selection (SP pin) .................................................22
3.5.1.5 Tx Amplitude Trim..................................................................................23
3.5.2 Software Mode.......................................................................................................23
3.5.2.1 Serial Input Clock (SCLK) ......................................................................23
3.5.2.2 Chip Select Input (CS) ...........................................................................23
3.5.2.3 Serial Input Word (SDI)..........................................................................23
3.5.2.4 Serial Output Word (SDO) .....................................................................23
Serial System Interface.......................................................................................................25
Parallel System Interface ....................................................................................................25
Loopback Modes ................................................................................................................26
3.8.1 Local Loopback......................................................................................................26
3.8.2 Remote Loopback..................................................................................................26
3.2
3.3
3.4
3.5
3.6
3.7
3.8
4.0
Register Definitions.....................................................................................................................27
Cortina Systems
®
LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Page 3
LXT6155 Transceiver
Datasheet
249612, Revision 7.0
14 Feburary 2007
Figures
5.0
Application Information ..............................................................................................................34
5.1
5.2
Fiber Optic Module Interface ..............................................................................................34
Coax Interface ....................................................................................................................35
6.0
7.0
Test Specifications ......................................................................................................................38
Mechanical Specifications ..........................................................................................................50
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LXT6155 Transceiver Block Diagram .............................................................................................. 8
LXT6155 Transceiver Pin Assignments .......................................................................................... 9
LXT6155 Transceiver System Interface ........................................................................................14
Example of CMI Encoded Binary Signal........................................................................................15
Receive Frame Synchronization and Frame Pulse Position .........................................................17
Framing State ................................................................................................................................18
Criteria for LOS Output ..................................................................................................................18
Hardware Mode .............................................................................................................................21
Software Mode ..............................................................................................................................24
Serial Data Output Word Structure (Read Cycle: R/W=High) .......................................................24
Serial Data Input Word Structure (Write Cycle: R/W = Low) .........................................................24
Serial Interface ..............................................................................................................................25
Parallel Interface............................................................................................................................25
Local Loopback .............................................................................................................................26
Remote Loopback .........................................................................................................................26
3.3 V LVPECL to 3.3 V LVPECL Interface ....................................................................................35
75 Ohm Coax Cable Interface .......................................................................................................36
Transmit Parallel Input Data Timing ..............................................................................................39
Transmit Serial Input Data Timing .................................................................................................40
Receive Serial Output Data Timing ...............................................................................................41
Receive Parallel Output Data Timing ............................................................................................42
Microprocessor Input Timing Diagram...........................................................................................44
Microprocessor Output Timing Diagram ........................................................................................44
CMI Encoded Zero per G.703 and STS-3 .....................................................................................45
CMI Encoded One per G.703 and STS-3 ......................................................................................46
Jitter Tolerance (template Values from
Table 34)
.........................................................................47
Jitter Generation Measurement Filter Characteristics ...................................................................48
Typical Coax Jitter Transfer...........................................................................................................48
Typical Fiber Jitter Transfer ...........................................................................................................49
LXT6155 Transceiver LE Package Specification ..........................................................................50
Tables
1
2
3
4
5
6
7
Pin Descriptions.............................................................................................................................10
Standards Compliance ..................................................................................................................15
Reference Clock Settings ..............................................................................................................21
Loopback Selection .......................................................................................................................22
MODE Line Interface Settings .......................................................................................................22
Device Address/Control Byte.........................................................................................................27
LXT6155 Transceiver Register Map (A<3:0>) ...............................................................................27
Cortina Systems
®
LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Page 4
LXT6155 Transceiver
Datasheet
249612, Revision 7.0
14 Feburary 2007
Tables
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
Primary Control Register Settings, Register #0 (Address A<3:0>=0000)......................................28
Tx Control, Register #1 (Address A<3:0>=0001) ..........................................................................28
Transmit PLL1, Register #2 (Address A<3:0>=0010)....................................................................29
Transmit PLL2, Register #3 (Address A<3:0>=0011)....................................................................29
Equalizer Load, Register #4 (Address A<3:0>=0100) ...................................................................29
Equalizer & AGC, Register #5 (Address A<3:0>=0101)................................................................29
Matching Filter 2, Register #6 (Address A<3:0>=0110) ................................................................30
Slicer, Register #7 (Address A<3:0>=0111) ..................................................................................30
RxPLL 1, Register #8 (Address A<3:0>=1000) .............................................................................30
Rx PLL 2, Register #9 (Address A<3:0>=1001) ............................................................................31
Test, Register #10 (Address A<3:0>=1010) ..................................................................................31
Register, Bias and Fuse Controls, Register #11 (Address A<3:0>=1011) ....................................31
Rx Digital 1, Register #12 (Address A<3:0>=1100).......................................................................32
Rx Digital 2, Register #13 (Address A<3:0>=11001).....................................................................32
Status Control, Register #14 (Address A<3:0>=1110) ..................................................................33
Read-Only Register #15 (Address A<3:0>=1111).........................................................................33
Transformer Specifications ............................................................................................................36
Crystal Specifications ....................................................................................................................37
Absolute Maximum Ratings ...........................................................................................................38
Recommended Operating Conditions ...........................................................................................38
DC Electrical Characteristics (Vcc = 3.0 V to 3.6 V; TA = -40 °C to 85 °C)...................................38
Transmit Timing Characteristics ....................................................................................................39
Transmit Analog Characteristics....................................................................................................40
Receive Timing Characteristics .....................................................................................................41
Receive Analog Characteristics.....................................................................................................42
Serial Control Timing .....................................................................................................................43
Jitter Tolerance Template (in UIpp) ...............................................................................................46
Jitter Generation ............................................................................................................................47
Jitter Transfer ................................................................................................................................47
LXT6155 Transceiver LE Package Specification (64-Pin Low-Profile Quad Flat Pack) ................50
Cortina Systems
®
LXT6155 155 Mbps SDH/SONET/ATM Transceiver
Page 5
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