IS43R16320A
32Meg x 16
512-MBIT DDR SDRAM
FEATURES
DEVICE OVERVIEW
ISSI
NOVEMBER 2006
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Clock Frequency: 166, 200 MHz
Power supply (V
DD
and V
DDQ
)
DDR 333: 2.5V + 0.2V
DDR 400: 2.6V + 0.1V
SSTL 2 interface
Four internal banks to hide row Pre-charge
and Active operations
Commands and addresses register on positive
clock edges (CK)
Bi-directional Data Strobe signal for data cap-
ture
Differential clock inputs (CK and
CK)
for
two data accesses per clock cycle
Data Mask feature for Writes supported
DLL aligns data I/O and Data Strobe transitions
with clock inputs
Programmable burst length for Read and Write
operations
Programmable CAS Latency
2/2.5 (6K), 2.5/3 (5T)
Programmable burst sequence: sequential or
interleaved
Burst concatenation and truncation supported
for maximum data throughput
Auto Pre-charge option for each Read or Write
burst
8192 refresh cycles every 64ms
Auto Refresh and Self Refresh Modes
Pre-charge Power Down and Active Power
Down Modes
Lead-free package
ISSI’s 512-Mbit DDR SDRAM achieves high-speed data
transfer using pipeline architecture and two data word
accesses per clock cycle. The 536,870,912-bit memory
array is internally organized as four banks of 128M-bit to
allow concurrent operations. The pipeline allows Read
and Write burst accesses to be virtually continuous, with
the option to concatenate or truncate the bursts. The
programmable features of burst length, burst sequence
and CAS latency enable further advantages. The device
is available in 16-bit data word size. Input data is regis-
tered on the I/O pins on both edges of Data Strobe
signal(s), while output data is referenced to both edges of
Data Strobe and both edges of CK. Commands are
registered on the positive edges of CK. Auto Refresh,
Active Power Down, and Pre-charge Power Down modes
are enabled by using clock enable (CKE) and other
inputs in an industry-standard sequence. All input and
output voltage levels are compatible with SSTL 2.
KEY TIMING PARAMETERS
Parameter
Clock Cycle Time
CAS
Latency = 3
CAS
Latency = 2.5
CAS
Latency = 2
Clock Frequency
CAS
Latency = 3
CAS
Latency = 2.5
CAS
Latency = 2
-5
-6
Unit
DDR400 DDR333
5
6
—
6
7.5
—
166
133
ns
ns
ns
MHz
MHz
MHz
200
166
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
11/10/06
1
IS43R16320A
Burst Definition
Burst Length
Starting Column Address
A2
A1
A0
0
2
0
0
4
1
1
0
0
0
0
8
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
Order of Accesses Within a Burst
Type = Sequential
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
ISSI
Type = Interleaved
0-1
1-0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
®
Notes:
1. For a burst length of two, A1-A i selects the two-data-element block; A0 selects the first access within the block.
2. For a burst length of four, A2-A i selects the four-data-element block; A0-A1 selects the first access within the block.
3. For a burst length of eight, A3-A i selects the eight-data- element block; A0-A2 selects the first access within the block.
4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type
and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the start-
ing column address, as shown in
Burst Definition.
Read Latency
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and the availability
of the first burst of output data. The latency can be programmed 2 or 2.5 clocks for DDR333, and 3 clocks for DDR400.
If a Read command is registered at clock edge n, and the latency is
m
clocks, the data is available nominally coincident with
clock edge
n +
m.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
11/10/06
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