CY14B101L
1 Mbit (128K x 8) nvSRAM
Features
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Functional Description
The Cypress CY14B101L is a fast static RAM with a nonvolatile
element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent, nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down. On
power up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control.
25 ns, 35 ns, and 45 ns Access Times
Pin compatible with STK14CA8
Hands off Automatic STORE on Power Down with only a small
Capacitor
STORE to QuantumTrap Nonvolatile Elements is initiated by
software, hardware, or AutoStore on Power Down
RECALL to SRAM initiated by Software or Power Up
Unlimited READ, WRITE, and RECALL Cycles
200,000 STORE Cycles to QuantumTrap
20 year Data Retention at 55°C
Single 3V +20%, –10% Operation
Commercial and Industrial Temperature
32-pin (300 mil) SOIC and 48-pin (300 mil) SSOP packages
RoHS Compliance
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Logic Block Diagram
A
5
A
6
A
7
A
8
A
9
A
12
A
13
A
14
A
15
A
16
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QuantumTrap
1024 x 1024
STORE
RECALL
ew
V
CC
V
CAP
POWER
CONTROL
STORE/
RECALL
CONTROL
STATIC RAM
ARRAY
1024 X 1024
ROW DECODER
m
D
HSB
SOFTWARE
DETECT
COLUMN IO
COLUMN DEC
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R
DQ
0
DQ
2
DQ
4
DQ
3
INPUT BUFFERS
DQ
1
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A
15
-
A
0
DQ
5
DQ
6
DQ
7
A
0
A
1
A
2
A
3
A
4
A
10
A
11
OE
CE
WE
Cypress Semiconductor Corporation
Document Number: 001-06400 Rev. *K
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 19, 2009
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CY14B101L
Contents
Features ............................................................................... 1
Functional Description ....................................................... 1
Logic Block Diagram .......................................................... 1
Contents .............................................................................. 2
Pinouts ................................................................................ 3
Device Operation ................................................................ 4
SRAM Read ......................................................................... 4
SRAM Write ......................................................................... 4
AutoStore Operation .......................................................... 4
Hardware STORE (HSB) Operation ................................... 4
Hardware RECALL (Power Up) .......................................... 5
Software STORE ................................................................. 5
Software RECALL ............................................................... 5
Data Protection ................................................................... 5
Noise Considerations ......................................................... 5
Low Average Active Power ................................................ 5
Preventing Store ................................................................. 6
Best Practices ..................................................................... 6
Maximum Ratings ............................................................... 8
Operating Range ................................................................. 8
DC Electrical Characteristics ............................................ 8
Data Retention and Endurance ......................................... 8
Capacitance ........................................................................ 9
Thermal Resistance ............................................................ 9
AC Test Conditions ............................................................ 9
SRAM Read Cycle ...................................................... 10
SRAM Write Cycle....................................................... 11
AutoStore or Power Up RECALL .................................... 12
Software Controlled STORE/RECALL Cycle .................. 13
Switching Waveforms ...................................................... 14
Part Numbering Nomenclature ........................................ 15
Ordering Information ........................................................ 15
These parts are not recommended for new designs. ... 15
Package Diagrams ............................................................ 17
Sales, Solutions, and Legal Information ........................ 20
Worldwide Sales and Design Support......................... 20
Products ...................................................................... 20
Document Number: 001-06400 Rev. *K
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CY14B101L
Pinouts
Figure 1. Pin Diagram - 32-Pin SOIC and 48-Pin SSOP
V
CAP
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A
15
HSB
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
V
CAP
A
16
A
14
A
12
A
7
A
6
A
5
NC
A
4
NC
NC
NC
V
SS
NC
NC
DQ0
A
3
A
2
A
1
A
0
DQ1
DQ2
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
48
47
46
45
44
43
42
41
40
39
38
37
36
35
V
CC
A
15
HSB
WE
A
13
A
8
A
9
NC
A
11
NC
NC
NC
V
SS
NC
NC
DQ6
OE
A
10
CE
DQ7
DQ5
DQ4
DQ3
V
CC
Top View
(not to scale)
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Pin Name
A
0
–A
16
DQ
0
-DQ
7
WE
CE
OE
V
SS
V
CC
HSB
Alt
I/O Type
Input
Input
Input
Input
Ground
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Table 1. Pin Definitions
Address Inputs.
Used to select one of the 131,072 bytes of the nvSRAM.
Write Enable Input, Active LOW.
When the chip is enabled and WE is LOW, data on the IO
pins is written to the specific address location.
Output Enable, Active LOW.
The active LOW OE input enables the data output buffers during
read cycles. Deasserting OE HIGH causes the IO pins to tri-state.
Ground for the Device.
The device is connected to ground of the system.
Input or Output
Bidirectional Data IO Lines.
Used as input or output lines depending on operation.
W
E
G
NC
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V
CAP
Power Supply
AutoStore Capacitor.
Supplies power to nvSRAM during power loss to store data from SRAM
to nonvolatile elements.
No Connect.
This pin is not connected to the die.
No Connect
Document Number: 001-06400 Rev. *K
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Input or Output
Hardware Store Busy (HSB).
When LOW, this output indicates a Hardware Store is in progress.
When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal
pull up resistor keeps this pin high if not connected (connection optional).
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Power Supply
Power Supply Inputs to the Device.
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Chip Enable Input, Active LOW.
When LOW, selects the chip. When HIGH, deselects the chip.
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Description
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CY14B101L
Device Operation
The CY14B101L nvSRAM is made up of two functional compo-
nents paired in the same physical cell. These are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation) or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture enables the storage and
recall of all cells in parallel. During the STORE and RECALL
operations, SRAM READ and WRITE operations are inhibited.
The CY14B101L supports unlimited reads and writes similar to
a typical SRAM. In addition, it provides unlimited RECALL opera-
tions from the nonvolatile cells and up to one million STORE
operations.
Figure 2
shows the proper connection of the storage capacitor
(V
CAP
) for automatic store operation. Refer to the
DC Electrical
Characteristics
on page 8 for the size of V
CAP
. The voltage on
the V
CAP
pin is driven to 5V by a charge pump internal to the chip.
A pull up is placed on WE to hold it inactive during power up.
Figure 2. AutoStore Mode
V
CC
V
CAP
V
CAP
V
CC
10k Ohm
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WE
SRAM Read
The CY14B101L performs a READ cycle whenever CE and OE
are LOW while WE and HSB are HIGH. The address specified
on pins A
0–16
determines the 131,072 data bytes accessed.
When the READ is initiated by an address transition, the outputs
are valid after a delay of t
AA
(READ cycle 1). If the READ is
initiated by CE or OE, the outputs are valid at t
ACE
or at t
DOE
,
whichever is later (READ cycle 2). The data outputs repeatedly
respond to address changes within the t
AA
access time without
the need for transitions on any control input pins, and remains
valid until another address change or until CE or OE is brought
HIGH, or WE or HSB is brought LOW.
SRAM Write
ec
The data on the common IO pins DQ
0–7
are written into the
memory if it has valid t
SD
, before the end of a WE controlled
WRITE or before the end of an CE controlled WRITE. Keep OE
HIGH during the entire WRITE cycle to avoid data bus contention
on common IO lines. If OE is left LOW, internal circuitry turns off
the output buffers t
HZWE
after WE goes LOW.
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A WRITE cycle is performed whenever CE and WE are LOW and
HSB is HIGH. The address inputs must be stable prior to entering
the WRITE cycle and must remain stable until either CE or WE
goes HIGH at the end of the cycle.
AutoStore Operation
The CY14B101L stores data to nvSRAM using one of three
storage operations:
1. Hardware store activated by HSB
2. Software store activated by an address sequence
3. AutoStore on device power down
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the CY14B101L.
During normal operation, the device draws current from V
CC
to
charge a capacitor connected to the V
CAP
pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
CC
pin drops below V
SWITCH
, the part
automatically disconnects the V
CAP
pin from V
CC
. A STORE
operation is initiated with power provided by the V
CAP
capacitor.
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Document Number: 001-06400 Rev. *K
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To reduce unnecessary nonvolatile stores, AutoStore and
Hardware Store operations are ignored, unless at least one
WRITE operation has taken place since the most recent STORE
or RECALL cycle. Software initiated STORE cycles are
performed regardless of whether a WRITE operation has taken
place. An optional pull-up resistor is shown connected to HSB.
The HSB signal is monitored by the system to detect if an
AutoStore cycle is in progress.
Hardware STORE (HSB) Operation
The CY14B101L provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB pin is used to
request a hardware STORE cycle. When the HSB pin is driven
LOW, the CY14B101L conditionally initiates a STORE operation
after t
DELAY
. An actual STORE cycle only begins if a WRITE to
the SRAM takes place since the last STORE or RECALL cycle.
The HSB pin also acts as an open drain driver that is internally
driven LOW to indicate a busy condition, while the STORE
(initiated by any means) is in progress. This pin should be exter-
nally pulled up if it is used to drive other inputs.
SRAM READ and WRITE operations, that are in progress when
HSB is driven LOW by any means, are given time to complete
before the STORE operation is initiated. After HSB goes LOW,
the CY14B101L continues SRAM operations for t
DELAY
. During
t
DELAY
, multiple SRAM READ operations take place. If a WRITE
is in progress when HSB is pulled LOW, it allows a time, t
DELAY
to complete. However, any SRAM WRITE cycles requested after
HSB goes LOW are inhibited until HSB returns HIGH.
If HSB is not used, it is left unconnected.
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CY14B101L
Hardware RECALL (Power Up)
During power up or after any low power condition (V
CC
<
V
SWITCH
), an internal RECALL request is latched. When V
CC
once again exceeds the sense voltage of V
SWITCH
, a RECALL
cycle is automatically initiated and takes t
HRECALL
to complete.
Data Protection
The CY14B101L protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and WRITE operations. The low voltage condition is detected
when V
CC
is less than V
SWITCH
.
If the CY14B101L is in a WRITE mode (both CE and WE are low)
at power up after a RECALL or after a STORE, the WRITE is
inhibited until a negative transition on CE or WE is detected. This
protects against inadvertent writes during power up or brown out
conditions.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The CY14B101L software
STORE cycle is initiated by executing sequential CE controlled
READ cycles from six specific address locations in exact order.
During the STORE cycle, an erase of the previous nonvolatile
data is first performed followed by a program of the nonvolatile
elements. When a STORE cycle is initiated, input and output are
disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other READ or WRITE
accesses intervene in the sequence. If they intervene, the
sequence is aborted and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following READ
sequence is performed:
1. Read address 0x4E38, Valid READ
2. Read address 0xB1C7, Valid READ
3. Read address 0x83E0, Valid READ
4. Read address 0x7C1F, Valid READ
5. Read address 0x703F, Valid READ
6. Read address 0x8FC0, Initiate STORE cycle
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CMOS technology provides the CY14B101L the benefit of
drawing significantly less current when it is cycled at times longer
than 50 ns.
Figure 3
shows the relationship between I
CC
and
READ or WRITE cycle time. Worst case current consumption is
shown for both CMOS and TTL input levels (commercial temper-
ature range, VCC = 3.6V, 100% duty cycle on chip enable). Only
standby current is drawn when the chip is disabled. The overall
average current drawn by the CY14B101L depends on the
following items:
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The software sequence is clocked with CE controlled READs or
OE controlled READs. When the sixth address in the sequence
is entered, the STORE cycle commences and the chip is
disabled. It is important that READ cycles and not WRITE cycles
are used in the sequence. It is not necessary that OE is LOW for
a valid sequence. After the t
STORE
cycle time is fulfilled, the
SRAM is again activated for READ and WRITE operation.
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Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of READ operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled READ operations is
performed:
1. Read address 0x4E38, Valid READ
2. Read address 0xB1C7, Valid READ
3. Read address 0x83E0, Valid READ
4. Read address 0x7C1F, Valid READ
5. Read address 0x703F, Valid READ
6. Read address 0x4C63, Initiate RECALL cycle
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Internally, RECALL is a two step procedure. First, the SRAM data
is cleared, and then the nonvolatile information is transferred into
the SRAM cells. After the t
RECALL
cycle time, the SRAM is once
again ready for READ and WRITE operations. The RECALL
operation does not alter the data in the nonvolatile elements. The
nonvolatile data can be recalled an unlimited number of times.
Document Number: 001-06400 Rev. *K
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IO loading
The duty cycle of chip enable
The overall cycle rate for accesses
The ratio of READs to WRITEs
CMOS versus TTL input levels
The operating temperature
The V
CC
level
Figure 3. Current Versus Cycle Time
ew
Low Average Active Power
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The CY14B101L is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between V
CC
and V
SS,
using leads and traces that are as short
as possible. As with all high speed CMOS ICs, careful routing of
power, ground, and signals reduce circuit noise.
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Noise Considerations
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